LOGIC COMMANDS AND REGISTERS NOTE: For SPI " />
參數(shù)資料
型號： KIT33742DWEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 42/71頁
文件大?。?/td> 0K
描述： KIT FOR 33742 SBC WITH EHSCAN
標準包裝： 1
主要目的： 接口，CAN 控制器
已用 IC / 零件： MC33742
相關(guān)產(chǎn)品： MC33742DW-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742DWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742SDW-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742SDWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
NOTE: For SPI Operation
In case a low pulse is asserted by the device on the RST output pin during a SPI message,
the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:
Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command
before the expiration of the timeout (in Normal mode or Normal Request mode and if the
“Timeout watchdog” option is selected), or the SPI watchdog refresh command is performed
in the closed window (in Normal mode and if “Window watchdog” option is selected).
Case 2: VDD undervoltage condition: VDD falls below the VDD undervoltage threshold.
Message corruption means that the targeted register address can be changed, and another
register is written. Table 15 shows the various cases and impacts on SPI register address:
Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:
write to CAN register can end up as write to MCR register, or
write to TIM1 register can end up as write to RCR register
To avoid the previously described behavior, it is recommended to write into the MCR, RCR,
CAN, and IOR registers with the expected configuration, after each RST assertion.
In the application, a RST low pulse leads to an MCU reset and a software restart. By
applying this recommendation, all registers will be written with the expected configuration.
IOR
$011
HS (high side switch) control in Normal
and Standby mode
HS over-temperature bit, VSUP, and V2
LOW status
WUR
$100
Control of wake-up input polarity
Wake-up input and real time Lx input
state
TIM
$101
TIM1: Watchdog timing control, Watch-
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
TIM2: Cyclic Sense and Forced Wake-
up timing selection
CANL and TXD failure reporting
LPC
$110
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-up mode
activation, CAN-INT mode selection
CANH and RXD failure reporting
INTR
$111
Enable or Disable of Interrupts
Interrupt source
Table 15. Possible Corrupted Registers In Case of RST Pulse During SPI Communication
Resulting Written register
Register
MCR
RCR
CAN
IOR
Address
$000
$001
$010
$011
Target
written
register
Register
Address
CAN
$010
X
IOR
$011
X
WUR
$100
X
TIM1/2
$101
X
LPC
$110
X
INTR
$111
X
Table 14. List of Registers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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KIT3376MMA7331L 功能描述:加速傳感器開發(fā)工具 3-AXIS ANALOG OUT 4g /12g Dev Kit RoHS:否 制造商:Murata 工具用于評估:SCA3100-D04 加速:2 g 傳感軸:Triple Axis 接口類型:SPI 工作電壓:3.3 V
KIT3376MMA7331LC 功能描述:加速傳感器開發(fā)工具 3AXIS Angl Accelero Eval Kit RoHS:否 制造商:Murata 工具用于評估:SCA3100-D04 加速:2 g 傳感軸:Triple Axis 接口類型:SPI 工作電壓:3.3 V
KIT3376MMA7340L 功能描述:加速傳感器開發(fā)工具 XYZ-AXIS ANALOG ACCELERO RoHS:否 制造商:Murata 工具用于評估:SCA3100-D04 加速:2 g 傳感軸:Triple Axis 接口類型:SPI 工作電壓:3.3 V
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