參數(shù)資料
型號： KIT33742DWEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 55/71頁
文件大?。?/td> 0K
描述： KIT FOR 33742 SBC WITH EHSCAN
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，CAN 控制器
已用 IC / 零件： MC33742
相關(guān)產(chǎn)品： MC33742DW-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742DWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742SDW-ND - IC SYSTEM BASE W/LIN 28-SOIC
MC33742SDWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
59
33742
TYPICAL APPLICATIONS
Figure 33. Power up sequence, No W/D write at first
POWER UP AND VDD GOING LOW WITH STOP MODE AS DEFAULT LOW POWER MODE IS SELECTED
The first part of Figure 34 is identical to Figure 33. If VDD is pulled below VDD under-voltage reset (typ 4.6 V), say by an over-
current or short-circuit (for instance, short to 4.0 V), and if a low power mode previously selected was Stop mode, the 33742
enters Reset mode (RST pin is active). The WDOG pin stays HIGH, but the high level (Voh) follows V1 level. The INT pin goes
LOW.
When the VDD overload condition is removed, the 33742 restarts in Normal Request mode.
Figure 34. Under-voltage on VDD
VDD
SPI (CS)
WD
RST
INT
SBC in
Reset
mode
350ms
SBC in Normal Request
& Reset modes
Reset each 350 ms
SBC in Normal
mode
SBC in Normal
Request & Reset
mode
Watchdog Refresh
Missing Watchdog Refresh
Watchdog
Refresh
VDD
SPI (CS)
WD
RST
INT
SBC in
Reset
mode
SBC in Normal Request
& Reset modes
Reset each 350 ms
SBC in Normal
mode
SBC in Normal
Reset mode
350 ms
Watchdog Refresh
Under-voltage at VDD (VDD < VRSTTH)
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