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參數(shù)資料
| 型號： | KSZ8841-PMQL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 35/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION KSZ8841-PMQL |
| 標準包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8841-PMQL |
| 主要屬性： | 1 個端口，100BASE-TX/10BASE-T |
| 次要屬性： | PCI 接口，LinkMD 線纜診斷 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 1114 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP 576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP |
| 其它名稱： | 576-1633 |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
40
M9999-100407-1.5
MAC Multicast Table 1 Register (MTR1 Offset 0x0024)
The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the
CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the
register.
Bit
Default
Read/
Write
Description
31-0
0x00000000
RW
MTR0 Multicast Table 1
When appropriate bit is set, the packet received with DA matches the
CRC hashing function is received without being filtered.
Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in
the RXCR then all multicast addresses are received regardless of the
multicast table value.
Interrupt Enable Register (INTEN Offset 0x0028)
This register enables the interrupts from the internal or external sources.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31
0
RW
DMLCIE DMA MAC Link Changed Interrupt Enable
When this bit is set, the DMA MAC Link Changed Interrupt is enabled.
When this bit is reset, the DMA MAC Link Changed Interrupt is
disabled.
30
0
RW
DMTIE DMA MAC Transmit Interrupt Enable
When this bit is set, the DMA MAC Transmit Interrupt is enabled.
When this bit is reset, the DMA MAC Transmit Interrupt is disabled.
29
0
RW
DMRIE DMA MAC Receive Interrupt Enable
When this bit is set, the DMA MAC Receive Interrupt is enabled.
When this bit is reset, the DMA MAC Receive Interrupt is disabled.
28
0
RW
DMTBUIE DMA MAC Transmit Buffer Unavailable Interrupt Enable
When this bit is set, the DMA MAC Transmit Buffer Unavailable
Interrupt is enabled.
When this bit is reset, the DMA MAC Transmit Buffer Unavailable
Interrupt is disabled.
27
0
RW
DMRBUIE DMA MAC Receive Buffer Unavailable Interrupt Enable
When this bit is set, the DMA MAC Receive Buffer Unavailable Interrupt
is enabled.
When this bit is reset, the DMA MAC Receive Buffer Unavailable
Interrupt is disabled.
26
0
RW
DMTPSIE DMA MAC Transmit Process Stopped Interrupt Enable
When this bit is set, the DMA MAC Transmit Process Stopped Interrupt
is enabled.
When this bit is reset, the DMA MAC Transmit Process Stopped
Interrupt is disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8841-PMQLI | 功能描述:以太網(wǎng) IC Single Ethernet Port + 32-bit/33MHz PCI interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface |
| KSZ8842-16 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_1 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
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