參數(shù)資料
型號: KSZ8841-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 42/74頁
文件大小: 0K
描述: BOARD EVALUATION KSZ8841-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8841-PMQL
主要屬性: 1 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: PCI 接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP
576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP
其它名稱: 576-1633
Micrel, Inc.
KSZ8841-PMQL
October 2007
47
M9999-100407-1.5
Bit
Default
R/W
Description
A “1” indicates that the function requires a device specific initialization
sequence following transition to the D0 uninitialization state.
The value of this bit is loaded from the PME_DSI bit in the EEPROM
0X6 word.
4
0
RO
Reserved
3
0
RO
PME Clock
When this bit is a “1”, it indicates that the function relies on the
presence of the PCI clock for PME# operation. When this bit is a “0”, it
indicates that no PCI clock is required for the function to generate
PME#.
The value of this bit is loaded from the PME_CK bit in the EEPROM
0x6 word.
2 - 0
0
RO
Power Management PCI Version
The value of this bit is loaded from the PME_VER[2:0] bits in the
EEPROM 0x6 word.
Wakeup Frame Control Register (Offset 0x021A): WFCR
This register holds control information programmed by the CPU to control the transmit module function.
Bit
Default
R/W
Description
15 - 8
0x00
RO
Reserved
7
0
RW
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
6 - 4
0x0
RO
Reserved
3
0
RW
WF3E
Wake up Frame 3 Enable
When set, it enables the wake up frame 3 pattern detection.
When reset, the wake up frame pattern detection is disabled.
2
0
RW
WF2E
Wake up Frame 2 Enable
When set, it enables the wake up frame 2 pattern detection.
When reset, the wake up frame pattern detection is disabled.
1
0
RW
WF1E
Wake up Frame 1 Enable
When set, it enables the wake up frame 1 pattern detection.
When reset, the wake up frame pattern detection is disabled.
0
RW
WF0E
Wake up Frame 0 Enable
When set, it enables the wake up frame 0 pattern detection.
When reset, the wake up frame pattern detection is disabled.
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