參數(shù)資料
型號： KSZ8842-16MVLI
廠商： Micrel Inc
文件頁數(shù)： 105/141頁
文件大?。?/td> 0K
描述： IC ETHERNET SW 2PORT BUS 128LQFP
標準包裝： 90
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱： 576-2120
KSZ8842-16MVLI-ND
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
66
M9999-102207-1.9
Bit
Default Value
R/W
Description
6
0x0
RW
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including
broadcast frames).
5
0x0
RW
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit
Station MAC address of the module.
4
0x0
RW
RXRA Receive All
When this bit is set, the KSZ8842M receives all incoming frames, regardless of the
frame’s destination address.
3
0x0
RW
RXSCE Receive Strip CRC
When this bit is set, the KSZ8842M strips the CRC on the received frames. Once
cleared, the CRC is stored in memory following the packet.
2
0x0
RW
QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that
pass the CRC Hash filtering mechanism.
1
-
RO
Reserved
0
0x0
RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state. When
reset, the receive process is placed in the stopped state upon completing reception of
the current frame.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved
12-0
-
RO
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is
used for both frame payload, control word. There is total 4096 bytes in TXQ.
Note: Software must be written to ensure that there is enough memory for the next
transmit frame including control information before transmit data is written to the TXQ.
Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount of receive data available in the RXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved
12-0
-
RO
RXMA Receive Packet Data Available
The amount of Receive packet data available is represented in units of byte. The RXQ
memory is used for both frame payload, status word. There is total 4096 bytes in RXQ.
This counter will update after a complete packet is received and also issues an
interrupt when receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to allow for the new RX
frame. If this is not done, the frame may be discarded as a result of insufficient RXQ
memory.
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KSZ8842-32 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
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KSZ8842-32MVL 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + Generic (32-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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