參數(shù)資料
型號: KSZ8842-16MVLI
廠商: Micrel Inc
文件頁數(shù): 113/141頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT BUS 128LQFP
標(biāo)準(zhǔn)包裝: 90
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱: 576-2120
KSZ8842-16MVLI-ND
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
73
M9999-102207-1.9
Bank 19 Multicast Table Register 3 (0x06): MTR3
Multicast table register 3.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
MTR0 Multicast Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR,
all multicast addresses are received regardless of the multicast table value.
Banks 20 – 31: Reserved
Except Bank Select Register (0xE).
Bank 32 Switch ID and Enable Register (0x00): SIDER
This register contains the switch ID and the switch enable control.
Bit
Default
R/W
Description
15-8
0x88
RO
Family ID
Chip family ID
7-4
0x0
RO
Chip ID
0x0 is assigned to KSZ8842M
3-1
0x1
RO
Revision ID
0
RW
Start Switch
1 = start the chip.
0 = switch is disabled.
Bank 32 Switch Global Control Register 1 (0x02): SGCR1
This register contains the global control for the switch function.
Bit
Default
R/W
Description
15
0
RW
Pass All Frames
1 = switch all packets including bad ones. Used solely for debugging purposes. Works
in conjunction with Sniffer mode only.
14
0
RW
Reserved
13
1
RW
IEEE 802.3x Transmit Direction Flow Control Enable
1 = enables transmit direction flow control feature.
0 = will not enable transmit direction flow control feature. The switch will not generate
any flow control packets.
12
1
RW
IEEE 802.3x Receive Direction Flow Control Enable
1 = enables receive direction flow control feature.
0 = will not enable receive direction flow control feature. The switch will not react to
any received flow control packets.
11
0
RW
Frame Length Field Check
1 = checks frame length field in the IEEE packets. If the actual length does not match,
the packet will be dropped (for Length/Type field < 1500).
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