參數(shù)資料
型號: KSZ8842-16MVLI
廠商: Micrel Inc
文件頁數(shù): 61/141頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT BUS 128LQFP
標(biāo)準(zhǔn)包裝: 90
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱: 576-2120
KSZ8842-16MVLI-ND
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
26
M9999-102207-1.9
Pin Number
Pin Name
Type
Pin Function
54
AGND
Gnd
Analog ground
55
TXM2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
56
TXP2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
57
VDDA
P
1.2 analog VDD input power supply from VDDCO (pin24) through external Ferrite
bead and capacitor.
58
AGND
Gnd
Analog ground
59
NC
Ipu
No connect
60
NC
Ipu
No connect
61
ISET
O
Set physical transmits output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
Gnd
Analog ground
63
VDDAP
P
1.2V analog VDD for PLL input power supply from VDDCO (pin24) through
external Ferrite bead and capacitor.
64
AGND
Gnd
Analog ground
65
X1
I
25MHz crystal or oscillator clock connection.
66
X2
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is a no connect.
Note: Clock is
± 50ppm for either crystal or oscillator.
67
RSTN
Ipu
Hardware reset pin (active Low). This reset input is required minimum of 10ms
low after stable supply voltage 3.3V.
68
A15
I
Address 15
69
A14
I
Address 14
70
A13
I
Address 13
71
A12
I
Address 12
72
A11
I
Address 11
73
A10
I
Address 10
74
A9
I
Address 9
75
A8
I
Address 8
76
A7
I
Address 7
77
A6
I
Address 6
78
DGND
Gnd
Digital IO ground
79
VDDIO
P
3.3V digital VDDIO input power supply for IO with well decoupling capacitors.
80
A5
I
Address 5
81
A4
I
Address 4
82
A3
I
Address 3
83
A2
I
Address 2
84
A1
I
Address 1
85
BE3N
I
Byte Enable 3 Not, Active low for Data byte 3 enable.
86
BE2N
I
Byte Enable 2 Not, Active low for Data byte 2 enable.
87
BE1N
I
Byte Enable 1 Not, Active low for Data byte 1 enable.
88
BE0N
I
Byte Enable 0 Not, Active low for Data byte 0 enable.
89
D31
I/O
Data 31
90
DGND
Gnd
Digital core ground
91
VDDC
P
1.2V digital core VDD input power supply from VDDCO (pin24) through external
Ferrite bead and capacitor.
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