參數(shù)資料
型號： KSZ8842-16MVLI
廠商： Micrel Inc
文件頁數(shù)： 46/141頁
文件大?。?/td> 0K
描述： IC ETHERNET SW 2PORT BUS 128LQFP
標(biāo)準(zhǔn)包裝： 90
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱： 576-2120
KSZ8842-16MVLI-ND
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
14
M9999-102207-1.9
Pin Number
Pin Name
Type
Pin Function
12
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
13
NC
Ipu
No connect.
14
NC
Opu
No connect.
15
SRDYN
Opu
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8842M drives this pin low to
signal wait states.
16
INTRN
Opd
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this pin
need an external 4.7K pull-up resistor.
17
LDEVN
Opd
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8842M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
18
RDN
Ipd
Read Strobe Not
Asynchronous read strobe, active Low.
19
EECS
Opu
EEPROM Chip Select
20
ARDY
Opd
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock. This pin need an
external 4.7K pull-up resistor.
21
CYCLEN
Ipd
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal
the command cycle.
For burst mode (32-bit interface only), this pin stays High for read cycles and
Low for write cycles.
22
P2LED3
Opd
Port 2 LED indicator
See the description in pins 6, 7, and 8.
23
DGND
Gnd
Digital IO ground
24
VDDCO
P
1.2V digital core voltage output (internal 1.2V LDO power supply output), this
1.2V output pin provides power to VDDC, VDDA and VDDAP pins.
Note: Internally generated power voltage. Do not connect an external power
supply to this pin. This pin is used for connecting external filter (Ferrite bead and
capacitors). It is recommended this pin should be connected to 3.3V power rail
by a 100 ohm resistor for the internal LDO application.
25
VLBUSN
Ipd
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or
EISA-like burst mode.
26
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
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KSZ8842-32 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
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