參數(shù)資料
型號： KSZ8842-16MVLI
廠商： Micrel Inc
文件頁數(shù)： 86/141頁
文件大?。?/td> 0K
描述： IC ETHERNET SW 2PORT BUS 128LQFP
標(biāo)準(zhǔn)包裝： 90
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱： 576-2120
KSZ8842-16MVLI-ND
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
49
M9999-102207-1.9
The format for ConfigParam is shown in Table 13.
Bit
Bit Name
Description
15 -2
Reserved
1
Clock_Rate
Internal clock rate selection
0: 125 MHz
1: 25 MHz
Note: At power up, this chip operates on 125 MHz clock. The internal frequency can be
dropped to 25 MHz via the external EEPROM.
0
ASYN_8bit
Async 8-bit or 16-bit bus select
1= bus is configured for 16-bit width
0= bus is configured for 8-bit width
(32-bit width, KSZ8842-32, don’t care this bit setting)
Table 13. ConfigParam Word in EEPROM Format
Loopback Support
The KSZ8842M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY
ports will be set to 100BASE-TX full-duplex mode. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
Far-end Loopback
Far-end loopback is conducted between the KSZ8842M’s two PHY ports. The loopback path starts at the “Originating.”
PHY port’s receive inputs (RXP/RXM), wraps around at the “l(fā)oopback” PHY port’s PMD/PMA, and ends at the
“Originating” PHY port’s transmit outputs (TXP/TXM).
Bit [8] of registers P1CR4 and P2CR4 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, Bit
[14] of registers P1MBCR and P2MBCR can also be used to enable far-end loopback. The port 2 far-end loopback path is
illustrated in the Figure 15.
Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of the KSZ8842M. The loopback path starts
at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY
port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers P1PHYCTRL and P2PHYCTRL is used to enable near-end loopback for ports 1 and 2, respectively.
Alternatively, Bit [9] of registers P1SCSLMD and P2SCSLMD can also be used to enable near-end loopback. The both
ports 1 and 2 near-end loopback paths are illustrated in the following Figure 16.
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