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參數(shù)資料
| 型號(hào)： | KSZ8842-PMBL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 46/119頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ETHERNT SW 2PORT PCI 100LFBGA |
| 特色產(chǎn)品： | Micrel Drives Ethernet Into the Global Automotive World |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 控制器類型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | PCI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 100-LFBGA |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1636-ND - BOARD EVALUATION KSZ8842-PMQL |
| 其它名稱： | 576-3089 |
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
32
M9999-100207-1.5
received at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if
the corresponding transmit queue is split. Bit 4 and 3 of registers P1CR1, P2CR1, and P3CR1 is used to enable port-
based priority for ports 1, 2, and the host port, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8842-PMQL/PMBL examines the ingress (incoming) packets to determine whether
they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority
mapping” value, as specified by the register SGCR6. The “priority mapping” value is programmable.
Figure 9 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Preamble
DA
TCI
76
6
2
length
Data
FCS
2
46-1500
4
S
F
D
1
Tagged Packet Type
(8100 for Ethernet)
802.1p
CFI
VLAN ID
Bytes
Bits
16
3
12
802.1q VLAN Tag
2
SA
VPID
1
Figure 9. 802.1p Priority Field Format
802.1p based priority is enabled by bit 5 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port,
respectively.
The KSZ8842-PMQL/PMBL provides the option to insert or remove the priority tagged frame's header at each individual
egress port. This header, consisting of the 2 bytes VLAN protocol ID (VPID) and the 2 bytes tag control information field
(TCI), is also referred to as the 802.1Q VLAN tag.
Tag insertion is enabled by bit 2 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port, respectively.
At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in
register sets P1VIDCR, P2VIDCR, AND P3VIDCR for ports 1, 2 and the host port, respectively. The KSZ8842-
PMQL/PMBL does not add tags to already tagged packets.
Tag removal is enabled by bit 1 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port, respectively.
At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8842-PMQL/PMBL will not
modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p priority field re-mapping is a QoS feature that allows the KSZ8842-PMQL/PMBL to set the “User Priority
Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority
field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority
Ceiling” is enabled by bit 3 of registers P1CR2, P2CR2, and P3CR2 for ports 1, 2, and the host port, respectively.
DiffServ based Priority
DiffServ-based priority uses the ToS registers shown in the Priority Control Registers section. The ToS priority control
registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to determine packet
priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully decoded, the
resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority.
Rate Limiting Support
The KSZ8842-PMQL/PMBL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive
side” and on the “transmit side” on a per port basis. For 10Base-T, a rate setting above 10 Mbps means the rate is not
limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate
Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by
setting up Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame
Gap) or Preamble byte, in addition to the data field (from packet DA to FCS).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8842-PMBL AM | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-PMBL AM TR | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-PMBLAM | 制造商:Micrel 功能描述:Ethernet Switch 2-Port 10Mbps/100Mbps |
| KSZ8842-PMBL-AM | 功能描述:Ethernet Switch 10/100 Base-T/TX PHY PCI Interface 制造商:microchip technology 系列:- 包裝:托盤(pán) 零件狀態(tài):要求報(bào)價(jià) 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:PCI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:3.1 V ~ 3.5 V 電流 - 電源:122mA 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LFBGA 供應(yīng)商器件封裝:* 標(biāo)準(zhǔn)包裝:260 |
| KSZ8842-PMBL-EVAL | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 2+1 Port 10/100 Ethernet Switch with 32b/33MHz PCI Interface (BGA Version) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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