參數(shù)資料
型號(hào): KSZ8842-PMBL
廠商: Micrel Inc
文件頁(yè)數(shù): 59/119頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNT SW 2PORT PCI 100LFBGA
特色產(chǎn)品: Micrel Drives Ethernet Into the Global Automotive World
標(biāo)準(zhǔn)包裝: 260
控制器類(lèi)型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LFBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
配用: 576-1636-ND - BOARD EVALUATION KSZ8842-PMQL
其它名稱(chēng): 576-3089
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
44
M9999-100207-1.5
Bit
Default
R/W
Description
9
0
RW
MTFCE MAC Transmit Flow Control Enable
When this bit is set, flow control is enabled. This causes the KSZ8842-
PMQL/PMBL to transmit a PAUSE frame from DMA to switch host MAC when
the Receive Buffer has reached threshold and this bit is enabled. (SGCR3 bit
5 also needs to be enabled).
Note: KSZ8842-PMQL/PMBL is full duplex only for RX/TX buffer.
8 – 3
0x0
RO
Reserved
2
0
RW
MTEP MAC DMA Transmit Enable Padding
When set, the KSZ8842-PMQL/PMBL automatically adds a padding field to a
packet shorter than 64 bytes.
Note: Setting this bit automatically enables Add CRC feature.
1
0
RW
MTAC MAC DMA Transmit Add CRC
When set, the KSZ8842-PMQL/PMBL appends the CRC to the end of the
transmission frame.
0
RW
MTE MAC DMA TX Enable
When the bit is set, the MDMA TX block is enabled and placed in a running
state. When reset, the transmission process is placed in the stopped state
after completing the transmission of the current frame. The stop transmission
command is effective only when the transmission process is in the running
state.
MAC DMA Receive Control Register (MDRXC Offset 0x0004)
The MAC DMA receive control register establishes the receive operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the receive initialization.
The following table shows the register bit fields.
Bit
Default
R/W
Description
31 – 30
00
RO
Reserved
29 – 24
0x00
RW
MRBS DMA Receive Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amount of data stored in the receive buffer before issuing a bus request. The
MRBS can be programmed with the following permissible values: 0,1, 2, 4, 8,
16, or 32.
After reset, the MRBS default is 0, i.e., unlimited.
23 – 19
0x0
RO
Reserved
18
0
RW
MRUCC MAC Receive UDP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct UDP checksum
for incoming UDP/IP frames at port.
Packets received with incorrect UDP checksum will be discarded.
17
0
RW
MRTCG MAC Receive TCP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct TCP checksum for
incoming TCP/IP frames at port.
Packets received with incorrect TCP checksum will be discarded.
16
0
RW
MRICG MAC Receive IP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct IP checksum for
incoming IP frames at port.
Packets received with incorrect IP checksum will be discarded.
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KSZ8842-PMBL AM 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842-PMBL AM TR 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842-PMBLAM 制造商:Micrel 功能描述:Ethernet Switch 2-Port 10Mbps/100Mbps
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KSZ8842-PMBL-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 2+1 Port 10/100 Ethernet Switch with 32b/33MHz PCI Interface (BGA Version) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: