Micrel, Inc.
KSZ8862-16/32MQL
April 2007
9
M9999-040407-3.0
List of Figures
Figure 1. KSZ8862M Functional Diagram ............................................................................................................................................... 1
Figure 2. 128-Pin PQFP ......................................................................................................................................................................... 11
Figure 3. 128-Pin PQFP ......................................................................................................................................................................... 17
Figure 4. Typical Straight Cable Connection ......................................................................................................................................... 26
Figure 5. Typical Crossover Cable Connection ...................................................................................................................................... 26
Figure 6. Auto Negotiation and Parallel Operation ................................................................................................................................. 27
Figure 7. Destination Address Lookup Flow Chart in Stage One .......................................................................................................... 30
Figure 8. Destination Address Resolution Flow Chart in Stage Two ..................................................................................................... 31
Figure 9. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8862M Bus ......................................................... 36
Figure 10. KSZ8862M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ................................................................................................. 37
Figure 11. 802.1p Priority Field Format .................................................................................................................................................. 44
Figure 12. Port 2 Far-End Loopback Path ............................................................................................................................................. 47
Figure 13. Port 1 and port 2 Near-End (Remote) Loopback Path.......................................................................................................... 47
Figure 14. Asynchronous Cycle – ADSN = 0....................................................................................................................................... 111
Figure 15. Asynchronous Cycle – Using ADSN................................................................................................................................... 112
Figure 16. Asynchronous Cycle – Using DATACSN ........................................................................................................................... 113
Figure 17. Address Latching Cycle for All Modes ................................................................................................................................ 114
Figure 18. Synchronous Burst Write Cycles – VLBUSN = 1................................................................................................................ 115
Figure 19. Synchronous Burst Read Cycles – VLBUSN = 1 ............................................................................................................... 116
Figure 20. Synchronous Write Cycle – VLBUSN = 0........................................................................................................................... 117
Figure 21. Synchronous Read Cycle – VLBUSN = 0........................................................................................................................... 118
Figure 22. EEPROM Read Cycle Timing Diagram .............................................................................................................................. 119
Figure 23. Auto-Negotiation Timing..................................................................................................................................................... 120
Figure 24. Reset Timing ...................................................................................................................................................................... 121
Figure 25. 128-Pin PQFP Package ..................................................................................................................................................... 123