參數(shù)資料
型號： KSZ8862-16MQL
廠商： Micrel Inc
文件頁數(shù)： 36/125頁
文件大?。?/td> 0K
描述： IC SWITCH 10/100 16BIT 128-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-1564
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
18
M9999-040407-3.0
Pin Description for KSZ8862-32 MQL (32-Bit)
Pin
Number
Pin Name
Type
Pin Function
1
TEST_EN
I
Test Enable
For normal operation, 1K ohm pull-down this pin-to-ground.
2
SCAN_EN
I
Scan Test Scan Mux Enable
For normal operation, 1K ohm pull-down this pin-to-ground.
3
P1LED2
Opu
4
P1LED1
Opu
5
P1LED0
Opu
6
P2LED2
Opu
7
P2LED1
Opu
8
P2LED0
Opu
Port 1 and Port 2 LED indicators
1 defined as follows:
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
[0,1]
P1LED3
2 /P2LED3
—
P1LED2/P2LED2
Link/Act
100Link/Act
P1LED1/P2LED1
Full duplex/Col
10Link/Act
P1LED0/P2LED0
Speed
Full duplex
Reg. SGCR5 bit [15,9]
[1,0]
[1,1]
P1LED3
2 /P2LED3
Act
—
P1LED2/P2LED2
Link
—
P1LED1/P2LED1
Full duplex/Col
—
P1LED0/P2LED0
Speed
—
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27. P2LED3 is pin 22.
9
DGND
Gnd
Digital ground
10
VDDIO
P
3.3V digital VDDIO input power supply for IO with well decoupling capacitors.
11
RDYRTNN
Ipd
Ready Return Not
For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the
host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.
12
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
13
DATACSN
Ipu
DATA Chip Select Not (For KSZ8862-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value of AEN,
A15-A1, and the content of the BANK select register.
14
NC
Opu
No connect.
15
SRDYN
Opu
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend
accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal is
synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal wait states.
16
INTRN
Opd
Interrupt
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