參數(shù)資料
型號： KSZ8862-16MQL
廠商： Micrel Inc
文件頁數(shù)： 37/125頁
文件大小： 0K
描述： IC SWITCH 10/100 16BIT 128-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-1564
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
19
M9999-040407-3.0
Pin
Number
Pin Name
Type
Pin Function
Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an
external 4.7K pull-up resistor.
17
LDEVN
Opd
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8862M address programmed into the high byte of the base address register. LDEVN
is a combinational decode of the Address and AEN signal.
18
RDN
Ipd
Read Strobe Not
Asynchronous read strobe, active Low.
19
EECS
Opu
EEPROM Chip Select
20
ARDY
Opd
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access cycles.
It is asynchronous to the host CPU or bus clock. This pin needs an external 4.7K pull-up
resistor.
21
CYCLEN
Ipd
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal the
command cycle.
For burst mode (32-bit interface only), this pin stays High for read cycles and Low for
write cycles.
22
P2LED3
Opd
Port 2 LED indicator. See the description in pins 6, 7, and 8.
23
DGND
Gnd
Digital IO ground
24
VDDCO
P
1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output
pin provides power to VDDC, VDDA and VDDAP pins.
Note: Internally generated power voltage. Do not connect an external power supply to this
pin. This pin is used for connecting external filter (Ferrite Bead and capacitors).
25
VLBUSN
Ipd
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like burst
mode.
26
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
27
P1LED3
Opd
Port 1 LED indicator
See the description in pins 3, 4, and 5.
28
EEDO
Opd
EEPROM Data Out
This pin is connected to DI input of the serial EEPROM.
29
EESK
Opd
EEPROM Serial Clock
A 4
s serial output clock to load configuration data from the serial EEPROM.
30
EEDI
Ipd
EEPROM Data In
This pin is connected to DO output of the serial EEPROM when EEEN is pull-up.
This pin can be pulled-down for 8-bit bus mode, pulled-up for 16-bus mode or either way
for 32-bus mode when EEEN is pulled-down (without EEPROM).
31
SWR
Ipd
Synchronous Write/Read
Write/Read signal for synchronous bus accesses. Write cycles when high and Read
cycles when low.
32
AEN
Ipu
Address Enable
Address qualifier for the address decoding, active Low.
33
WRN
Ipd
Write Strobe Not Asynchronous write strobe, active Low.
34
DGND
Gnd
Digital IO ground
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