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| 型號： | KSZ8863MLLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 73/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3867-ND - BOARD EVALUATION FOR KSZ8863MLL |
| 其它名稱： | 576-3751 |
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PIC16C72 Series
DS39016A-page 68
Preliminary
1998 Microchip Technology Inc.
10.10
Interrupts
The PIC16C72/CR72 has 8 sources of interrupt. The
interrupt control register (INTCON) records individual
interrupt requests in ag bits. It also has individual and
global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s ag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous
registers.
Individual
interrupt
bits
are
set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overow interrupt ags are con-
tained in the INTCON register.
The peripheral interrupt ags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt ag bits. The interrupt ag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt ag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
10.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
on
the
RB0/INT
pin,
ag
bit
INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 10.13 for details on SLEEP mode.
10.10.2 TMR0 INTERRUPT
An overow (FFh
→ 00h) in the TMR0 register will set
ag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
10.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets ag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
FIGURE 10-11: INTERRUPT LOGIC
Note:
Individual interrupt ag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
Clear GIE bit
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