參數(shù)資料
型號(hào)： KSZ8863MLLI
廠商： Micrel Inc
文件頁數(shù)： 76/106頁
文件大?。?/td> 0K
描述： IC ETHERNET SWITCH 3PORT 48-LQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： 576-3867-ND - BOARD EVALUATION FOR KSZ8863MLL
其它名稱： 576-3751
PIC16C72 Series
DS39016A-page 70
Preliminary
1998 Microchip Technology Inc.
10.12
Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
conguration bit WDTE (Section 10.1).
WDT time-out period values may be found in the Elec-
trical Specications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
.
FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Cong. bits
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
81h,181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 10-1 for operation of these bits.
From TMR0 Clock Source
To TMR0 (Figure 4-2)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
8
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