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參數(shù)資料
| 型號(hào)： | KSZ8995M |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 21/73頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 10/100 5PORT 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1607-ND - BOARD EVAL EXPERIMENT KSZ8995MA |
| 其它名稱： | 576-1038 |
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KS8995M
Micrel
M9999-120403
28
December 2003
The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These
interfaces are nibble wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators
that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates
a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not
provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the
physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this
configuration. For PHY mode operation, if the device interfacing with the KS8995M has an MRXER pin, it should be tied low.
For MAC mode operation, if the device interfacing with the KS8995M has an MTXER pin, it should be tied low.
SNI Interface Operation
The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. This
interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission
and the other for reception. The signals involved are described in Table 3.
SNI Signal
Description
KS8995M Signal
TXEN
Transmit enable
SMTXEN
TXD
Serial transmit data
SMTXD[0]
TXC
Transmit clock
SMTXC
COL
Collision detection
SCOL
CRS
Carrier sense
SMRXDV
RXD
Serial receive data
SMRXD[0]
RXC
Receive clock
SMRXC
Table 3. SNI Signals
This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the
transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
Advanced Functionality
Spanning Tree Support
To support spanning tree, port 5 is the designated port for the processor.
The other ports (port 1 - port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable”
and “l(fā)earning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3 and 4, respectively. The following
description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those
packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: the processor should not send any packets to the port(s) in this state. The processor should program the static
table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switch
will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor
may send packets to the port(s) in this state, see
“Special Tagging Mode” section for details. Address learning is disabled on
the port in this state.
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| KSZ8995MA | 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8995MA4 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KSZ8995MAB3 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KSZ8995MA-EVAL | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 KSZ8995MA Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8995MAI | 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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