參數(shù)資料
型號(hào): KSZ8995M
廠商: Micrel Inc
文件頁數(shù): 35/73頁
文件大小: 0K
描述: IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1607-ND - BOARD EVAL EXPERIMENT KSZ8995MA
其它名稱: 576-1038
KS8995M
Micrel
M9999-120403
40
December 2003
Address
Name
Description
Mode
Default
Register 2 (0x02): Global Control 0
7
Reserved
R/W
0x0
6-4
802.1p base priority
Used to classify priority for incoming 802.1q packets.
R/W
0x4
“User priority” is compared against this value.
≥ : classified as high priority.
< : classified as low priority.
3
Enable PHY MII
1, enable PHY MII interface.
R/W
Pin LED[5][1]
(Note: if not enabled, the switch will tri-state all outputs)
strap option.
Pull-down (0):
isolate. Pull-up
(1): Enable.
Note: LED[5][1]
has internal
pull-up.
2
Buffer share mode
1, buffer pool is shared by all ports. A port can use
R/W
0x1
more buffer when other ports are not busy.
0, a port is only allowed to use 1/5 of the buffer pool.
1
UNH mode
1 the switch will drop packets with 0x8808 in T/L
R/W
0
filed, or DA=01-80-C2-00-00-01.
0, the switch will drop packets qualified as
“flow control” packets.
0
Link change age
1, link change from “l(fā)ink” to “no link” will cause fast
R/W
0
aging (<800
s) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 + 75 seconds ). Note: If any port is
unplugged, all addresses will be automatically aged
out.
Register 3 (0x03): Global Control 1
7
Pass all frames
1, switch all packets including bad ones. Used solely
R/W
0
for debugging purpose. Works in conjunction with
sniffer mode.
6
Reserved
R/W
0
5
IEEE 802.3x Transmit
0, will enable transmit flow control based on AN result.
R/W
Pin PMRXD3
flow control disable
1, will not enable transmit flow control regardless of
strap option.
AN result.
Pull-down(0):
Enable tx flow
control. Pull-up (1):
Disable tx/rx
flow control.
Note: PMRXD3
has internal pull-
down.
4
IEEE 802.3x Receive
0, will enable receive flow control based on AN result.
R/W
Pin PMRXD3 strap
flow control disable
1, will not enable receive flow control regardless of
option. Pull-down
AN result.
(0): Enable rx flow
control. Pull-up (1):
Note: Bit 5 and bit 4 default values are controlled by
Disable tx/rx flow
the same pin, but they can be programmed
control.
independently.
Note: PMRXD3
has internal pull-
down.
3
Frame Length field check
1, will check frame length field in the IEEE packets.
R/W
0
If the actual length does not match, the packet will be
dropped. (for L/T < 1500)
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