- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4594 > KSZ8995M (Micrel Inc)IC SWITCH 10/100 5PORT 128PQFP PDF資料下載
參數(shù)資料
| 型號： | KSZ8995M |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 29/73頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH 10/100 5PORT 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1607-ND - BOARD EVAL EXPERIMENT KSZ8995MA |
| 其它名稱： | 576-1038 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
December 2003
35
M9999-120403
KS8995M
Micrel
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, the KS8995M can perform more advanced features like “broadcast storm protection,” “rate control,”
etc. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the
“Memory Map,”
except the status registers. After reset, the KS8995M will start to read all 110 registers sequentially from the EEPROM. The
configuration access time (t
prgm) is less than 15ms as shown in Figure 7.
....
RST_N
SCL
SDA
t prgm <15 ms
Figure 7. KS8995M EEPROM
Configuration Timing Diagram
To configure the KS8995M with a pre-configured EEPROM use the following steps:
1. At the board level, connect pin 110 on the KS8995M to the SCL pin on the EEPROM. Connect pin 111 on the
KS8995M to the SDA pin on the EEPROM.
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00”. This puts the KS8995M serial bus configuration
into I2C master mode.
3. Be sure the board level reset signal is connected to the KS8995M reset signal on pin 115 (RST_N).
4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other data
will be ignored.
5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KS8995M. After the reset is deasserted, the KS8995M will begin reading configuration data from the EEPROM. The
configuration access time (t
prgm) is less than 15ms.
Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KS8995M can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including “VLAN,”
“IGMP snooping,” “MIB counters,” etc. The external master device can access any register from register 0 to register 127
randomly. The system should configure all the desired settings before enabling the switch in the KS8995M. To enable the
switch, write a one to register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KS8995M also supports multiple reads or writes. After a byte is written to or read from the KS8995M,
the internal address counter automatically increments if the SPI Slave Select signal (SPIS_N) continues to be driven low. If
SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is kept
low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. Asserting
SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low again
before issuing another command and address. The address counter wraps back to zero once it reaches the highest address.
Therefore the entire register set can be written to or read from by issuing a single command and address.
The KS8995M is able to support a 5MHz SPI bus. A high performance SPI master is recommended to prevent internal counter
overflow.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RSM40DTAT | CONN EDGECARD 80POS R/A .156 SLD |
| LFEC6E-3QN208C | IC FPGA 6.1KLUTS 147I/O 208-PQFP |
| LFEC6E-3Q208C | IC FPGA 6.1KLUTS 147I/O 208-PQFP |
| RMM40DTAT | CONN EDGECARD 80POS R/A .156 SLD |
| LFXP3E-5Q208C | IC FPGA 3.1KLUTS 136I/O 208-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8995MA | 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8995MA4 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KSZ8995MAB3 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KSZ8995MA-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 KSZ8995MA Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8995MAI | 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。