參數(shù)資料
型號(hào)： LAMXO640E-3FTN256E
廠(chǎng)商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 10/77頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 640LUTS 256TQFP
標(biāo)準(zhǔn)包裝： 90
系列： LA-MachXO
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 4.9ns
電壓電源 - 內(nèi)部： 1.14 V ~ 1.26 V
宏單元數(shù)： 320
輸入/輸出數(shù)： 159
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA（17x17）
包裝： 托盤(pán)
2-15
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the LA-MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. LA-MachXO PIO Block Diagram
sysIO Buffer
Each I/O is associated with a exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the LA-MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are
powered using VCCIO. In addition to the Bank VCCIO supplies, the LA-MachXO devices have a VCC core logic power
supply, and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced
input buffers.
LA-MachXO256 and LA-MachXO640 devices contain single-ended input buffers and single-ended output buffers
with complementary outputs on all the I/O Banks.
LA-MachXO1200 and LA-MachXO2280 devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
PAD
sysIO
Buffer
TO
Programmable
Delay Elements
From Complementary
Pad
1
2
3
4
+
-
Input
Data Signal
From Routing
Fast Output
Note: Buffer 1 tracks with VCCAUX
Buffer 3 tracks with internal 1.2V VREF.
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
Buffer 2 tracks with VCCIO.
Data signal
TSALL
DO
TS
相關(guān)PDF資料
PDF描述
LAMXO640C-3FTN256E IC FPGA 640LUTS 256TQFP
TAP475M016SRW CAP TANT 4.7UF 16V 20% RADIAL
MIC5237-3.3BU IC REG LDO 3.3V .5A TO263
LCMXO1200E-5M132C IC PLD 1200LUTS 101I/O 132-BGA
MAX5900LAEUT+T IC HOT-SWAP CONTROLLER SOT23-6
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAMXO640E-3TN100E 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LAMXO640E-3TN144E 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LAMXO640LUTSC-3FTN256E 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet
LAMXO640LUTSC-3FTN324E 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet
LAMXO640LUTSC-3TN100E 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*