參數(shù)資料
型號: LAMXO640E-3FTN256E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 37/77頁
文件大小: 0K
描述: IC FPGA 640LUTS 256TQFP
標(biāo)準(zhǔn)包裝: 90
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 320
輸入/輸出數(shù): 159
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA(17x17)
包裝: 托盤
3-16
DC and Switching Characteristics
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
LA-MachXO “C” Sleep Mode Timing
Parameter
Descriptions
Conditions
Min.
Max.
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
25
420
MHz
fOUT
Output Clock Frequency (CLKOP, CLKOS)
25
420
MHz
fOUT2
K-Divider Output Frequency (CLKOK)
0.195
210
MHz
fVCO
PLL VCO Frequency
420
840
MHz
fPFD
Phase Detector Input Frequency
25
MHz
AC Characteristics
tDT
Output Clock Duty Cycle
Default duty cycle selected
3
45
55
%
tPH
4
Output Phase Accuracy
0.05
UI
tOPJIT
1
Output Clock Period Jitter
Fout ≥ 100MHz
+/-120
ps
Fout < 100MHz
0.02
UIPP
tSK
Input Clock to Output Clock Skew
Divider ratio = integer
+/-200
ps
tW
Output Clock Pulse Width
At 90% or 10%
3
1—
ns
tLOCK
2
PLL Lock-in Time
150
s
tPA
Programmable Delay Unit
100
450
ps
tIPJIT
Input Clock Period Jitter
+/-200
ps
tFBKDLY
External Feedback Delay
10
ns
tHI
Input Clock High Time
90% to 90%
0.5
ns
tLO
Input Clock Low Time
10% to 10%
0.5
ns
tRST
RST Pulse Width
10
ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output.
Rev. A 0.19
Symbol
Parameter
Device
Min.
Typ.
Max
Units
tPWRDN
SLEEPN Low to Power Down
All
400
ns
tPWRUP
SLEEPN High to Power Up
LCMXO256
400
s
LCMXO640
600
s
tWSLEEPN
SLEEPN Pulse Width
All
400
ns
tWAWAKE
SLEEPN Pulse Rejection
All
100
ns
Rev. A 0.19
SLEEPN
tPWRUP
Power Down Mode
tPWRDN
tWSLEEPN or tWAWAKE
I/O
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