參數(shù)資料
型號: LAMXO640E-3FTN256E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 32/77頁
文件大小: 0K
描述: IC FPGA 640LUTS 256TQFP
標準包裝: 90
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 320
輸入/輸出數(shù): 159
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應商設(shè)備封裝: 256-FTBGA(17x17)
包裝: 托盤
3-12
DC and Switching Characteristics
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Typical Building Block Function Performance
1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Derating Logic Timing
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case
numbers in the operating range. Actual delays may be much faster. The ispLEVER design tool from Lattice can pro-
vide logic timing numbers at a particular temperature and voltage.
Function
-3 Timing
Units
Basic Functions
16-bit decoder
9.4
ns
4:1 MUX
6.3
ns
16:1 MUX
7.1
ns
Function
-3 Timing
Units
Basic Functions
16:1 MUX
348
MHz
16-bit adder
209
MHz
16-bit counter
277
MHz
64-bit counter
143
MHz
Embedded Memory Functions (1200 and 2280 Devices Only)
256x36 Single Port RAM
203
MHz
512x18 True-Dual Port RAM
203
MHz
Distributed Memory Functions
16x2 Single Port RAM
310
MHz
64x2 Single Port RAM
229
MHz
128x4 Single Port RAM
186
MHz
32x2 Pseudo-Dual Port RAM
224
MHz
64x4 Pseudo-Dual Port RAM
194
MHz
1. The above timing numbers are generated using the ispLEVER design tool. Exact performance may vary with device and
tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
Rev. A 0.19
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