參數(shù)資料
型號: LHF16J06
廠商: Sharp Corporation
英文描述: Flash Memory 16M (1M 】 16 / 2M 】 8)
中文描述: 閃存16M內(nèi)存(100萬】16 / 2米】8)
文件頁數(shù): 19/47頁
文件大?。?/td> 245K
代理商: LHF16J06
LHF16J06
17
Rev. 1.26
Table 6. Status Register Definition
WBWSLBS
WSMS
BESS
ECBLBS
VCCWS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS (ECBLBS)
1 = Error in Block Erase, Full Chip Erase or Clear Block
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT
STATUS (WBWSLBS)
1 = Error in Word/Byte Write or Set Block/Permanent
Lock-Bit
0 = Successful Word/Byte Write or Set Block/Permanent
Lock-Bit
SR.3 = V
CCW
STATUS (VCCWS)
1 = V
CCW
Low Detect, Operation Abort
0 = V
CCW
OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#
Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
Check RY/BY# or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of V
CCW
level. The WSM interrogates and indicates the V
CCW
level
only after Block Erase, Full Chip Erase, Word/Byte Write or
Lock-Bit Configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when
V
CCW
V
CCWH1/2
.
SR.1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or WP# is V
IL
. Reading
the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
sharp
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