Bottom Boot
32KW/64KB Main Block 14
32KW/64KB Main Block 5
32KW/64KB Main Block 4
32KW/64KB Main Block 3
32KW/64KB Main Block 2
32KW/64KB Main Block 1
32KW/64KB Main Block 0
4KW/8KB Boot Block 1
4KW/8KB Boot Block 0
4KW/8KB Parameter Block 5
4KW/8KB Parameter Block 4
4KW/8KB Parameter Block 3
4KW/8KB Parameter Block 2
4KW/8KB Parameter Block 1
4KW/8KB Parameter Block 0
32KW/64KB Main Block 15
32KW/64KB Main Block 16
32KW/64KB Main Block 17
32KW/64KB Main Block 18
32KW/64KB Main Block 19
32KW/64KB Main Block 20
32KW/64KB Main Block 21
32KW/64KB Main Block 22
32KW/64KB Main Block 23
32KW/64KB Main Block 24
32KW/64KB Main Block 25
32KW/64KB Main Block 26
32KW/64KB Main Block 27
32KW/64KB Main Block 28
32KW/64KB Main Block 29
32KW/64KB Main Block 30
32KW/64KB Main Block 12
32KW/64KB Main Block 10
32KW/64KB Main Block 11
32KW/64KB Main Block 13
32KW/64KB Main Block 9
32KW/64KB Main Block 8
32KW/64KB Main Block 7
32KW/64KB Main Block 6
7FFFF
78000
70000
68000
60000
58000
50000
48000
47FFF
40000
38000
30000
2FFFF
28000
20000
18000
10000
0FFFF
08000
07FFF
07000
00000
01000
06000
05FFF
05000
04000
03000
02FFF
02000
98000
90000
88000
80000
C0000
B8000
B7FFF
B0000
A8000
9FFFF
E0000
D8000
D7FFF
D0000
C8000
C7FFF
FFFFF
F8000
F0000
E8000
E7FFF
[A
19
-A
0
]
[A
19
-A
-1
]
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
0F0000
0E0000
0D0000
0CFFFF
0C0000
0B0000
0A0000
090000
08FFFF
080000
070000
060000
05FFFF
050000
040000
030000
01FFFF
010000
00E000
000000
00C000
00BFFF
00A000
009FFF
008000
006000
004000
001FFF
13FFFF
130000
120000
110000
0FFFFF
170000
16FFFF
160000
150000
140000
1C0000
1B0000
1AFFFF
1A0000
190000
17FFFF
LHF16J06
7
Rev. 1.26
2 PRINCIPLES OF OPERATION
The LH28F160BJE-BTL90 flash memory includes an on-
chip WSM to manage block erase, full chip erase,
word/byte write and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erase, full chip erase, word/byte
write and lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
CCW
voltage. High
voltage on V
CCW
enables successful block erase, full chip
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contentsblock
erase, full chip erase, word/byte write, lock-bit
configuration, status and identifier codesare accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
Figure 3. Memory Map
sharp