參數(shù)資料
型號: LHF16J06
廠商: Sharp Corporation
英文描述: Flash Memory 16M (1M 】 16 / 2M 】 8)
中文描述: 閃存16M內(nèi)存(100萬】16 / 2米】8)
文件頁數(shù): 38/47頁
文件大?。?/td> 245K
代理商: LHF16J06
LHF16J06
36
Rev. 1.26
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
(1)
V
CC
=2.7V-3.6V, T
A
=0°C to +70°C
Parameter
Sym.
t
AVAV
t
PHEL
t
WLEL
t
ELEH
t
SHEH
t
VPEH
t
AVEH
t
DVEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHRL
t
EHGL
t
QVVL
t
QVSL
t
FVEH
t
EHFV
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A
IN
and D
IN
for block erase, full chip erase, word/byte write or lock-bit configuration.
4. V
CCW
should be held at V
CCWH1/2
until determination of block erase, full chip erase, word/byte write or lock-bit
configuration success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Notes
Min.
90
1
0
65
100
100
50
50
0
0
0
25
Max.
Unit
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
WP#V
IH
Setup to CE# Going High
V
CCW
Setup to CE# Going High
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to RY/BY# Going Low or SR.7 Going "0"
Write Recovery before Read
V
CCW
Hold from Valid SRD, RY/BY# High Z
WP# V
IH
Hold from Valid SRD, RY/BY# High Z
BYTE# Setup to CE# Going High
BYTE# Hold from CE# High
2
2
2
3
3
100
0
0
0
50
90
2,4
2,4
5
5
sharp
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