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參數(shù)資料
| 型號(hào)： | LM4550VH/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, LQFP-48 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 611K |
| 代理商： | LM4550VH/NOPB |
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AC Link Serial Interface Protocol
AC LINK OUTPUT FRAME:
SDATA_OUT, CONTROLLER OUTPUT TO LM4550 INPUT
The AC Link Output Frame carries control and PCM data to
the LM4550 control registers and stereo DAC. Output
Frames are carried on the SDATA_OUT signal which is an
output from the AC ’97 Digital Controller and an input to the
LM4550 codec. As shown in Figure 3, Output Frames are
constructed from thirteen time slots: one Tag Slot followed by
twelve Data Slots. Each Frame consists of 256 bits with each
of the twelve Data Slots containing 20 bits. Input and Output
Frames are aligned to the same SYNC transition. Note that
the LM4550 only accepts data in eight of the twelve Data
Slots and, since it is a two channel codec only in 4 simulta-
neously – 2 for control, one each for PCM data to the left and
right channel DACs. Data-Slot to DAC mappings are tied to
the codec mode selected by the Identity pins ID1#, ID0# and
are given in Table 1.
A new Output Frame is signaled with a low-to-high transition
of SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 4 and
Figure 5, the first tag bit in the Frame (“Valid Frame”) should
be clocked from the controller by the next rising edge of
BIT_CLK and sampled by the LM4550 on the following
falling edge. The AC ’97 Controller should always clock data
to SDATA_OUT on a rising edge of BIT_CLK and the
LM4550 always samples SDATA_OUT on the next falling
edge. SYNC is sampled with the rising edge of BIT_CLK.
The LM4550 checks each Frame to ensure 256 bits are
received. If a new Frame is detected (a low-to-high transition
on SYNC) before 256 bits are received from the old Frame
then the new Frame is ignored i.e. the data on SDATA_OUT
is discarded until a valid new Frame is detected.
The LM4550 expects to receive data MSB first, in an MSB
justified format.
SDATA_OUT: Slot 0 – Tag Phase
The first bit of Slot 0 is designated the "Valid Frame" bit. If
this bit is 1, it indicates that the current Output Frame con-
tains at least one slot of valid data and the LM4550 will check
further tag bits for valid data in the expected Data Slots. With
the codec in Primary mode, a controller will indicate valid
data in a slot by setting the associated tag bit equal to 1.
Since it is a two channel codec the LM4550 can only receive
10097204
FIGURE 3. AC Link Bidirectional Audio Frame
10097206
FIGURE 4. AC Link Output Frame
LM4550
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4550VHX | 制造商:Rochester Electronics LLC 功能描述:AC '97 REV 2.1 CODEC - Bulk |
| LM4550VHX/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP T/R |
| LM4558 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
| LM4558_08 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
| LM4558D | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
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