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參數(shù)資料
| 型號： | LM4550VH/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, LQFP-48 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大?。?/td> | 611K |
| 代理商： | LM4550VH/NOPB |
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Electrical Characteristics (Notes 1, 5) The following specifications apply for AV
DD = 5V, DVDD = 5V, Fs = 48
kHz, single codec configuration, unless otherwise noted. Limits apply for T
A= 25C. The reference for 0 dB is 1 Vrms unless
otherwise specified. (Continued)
Symbol
Parameter
Conditions
LM4550
Units
(Limits)
Typical
Limit
T
SSETUP
Setup Time for codec SYNC input
SYNC to rising edge of BIT_CLK
TBD
ns (min)
T
SHOLD
Hold Time for codec SYNC input
Hold time of SYNC from rising edge of
BIT_CLK
TBD
ns (min)
T
CO
Output Valid Delay
Output Delay of SDATA_IN from rising
edge of BIT_CLK
TBD
15
ns (max)
T
RISE
Rise Time
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
6
ns (max)
T
FALL
Fall Time
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
6
ns (max)
T
CS
Chain Propagation Delay
Data Delay from CIN to SDATA_IN
when the chain feature is active
TBD
ns (max)
T
RST_LOW
RESET# active low pulse width
For Cold Reset
1.0
s (min)
T
RST2CLK
RESET# inactive to BIT_CLK start
up
For Cold Reset
TBD
162.8
ns (min)
T
SH
SYNC active high pulse width
For Warm Reset
1.3
TBD
s (min)
T
SYNC2CLK
SYNC inactive to BIT_CLK start up
For Warm Reset
TBD
162.8
ns (min)
T
S2_PDOWN
AC Link Power Down Delay
Delay from end of Slot 2 to BIT_CLK,
SDATA_IN low
1
s (max)
T
SUPPLY2RST
Power On Reset
Time from minimum valid supply levels
to end of Reset
1
s (min)
T
SU2RST
Setup to trailing edge of RESET#
For ATE Test Mode
15
ns (min)
T
RST2HZ
Rising edge of RESET# to Hi-Z
For ATE Test Mode
25
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 2: Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 3: Machine Model, 220 pF – 240 pF discharged through all pins.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum
allowable power dissipation is PDMAX =(TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4550, TJMAX = 150C.
The typical junction-to-ambient thermal resistance is 74C/W for package number VBH48A.
Note 5: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 6: Typicals are measured at 25C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Loopthrough Mode describes a path from an analog input through the analog mixers to an analog output.
Note 9: These specifications are guaranteed by design and characterization; they are not production tested.
Note 10: Out of band energy is measured from 28.8 kHz to 100 kHz relative toa1Vrms DAC output.
LM4550
www.national.com
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4550VHX | 制造商:Rochester Electronics LLC 功能描述:AC '97 REV 2.1 CODEC - Bulk |
| LM4550VHX/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP T/R |
| LM4558 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
| LM4558_08 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
| LM4558D | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
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