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參數(shù)資料
| 型號(hào)： | LM4550VH/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, LQFP-48 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 611K |
| 代理商： | LM4550VH/NOPB |
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Register Descriptions (Continued)
Record Gain Register (1Ch)
Mute
Gx3:Gx0
Function
0
1111
22.5dB gain
0
0000
0dB gain
1
XXXX
*mute
Default: 8000h
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions imple-
mented on the LM4550. The miscellaneous control bits in-
clude POP which allows the DAC output to bypass the
National 3D Sound circuitry, 3D which enables or disables
the National 3D Sound circuitry, MIX which selects the MO-
NO_OUT source, MS which controls the Microphone Selec-
tion mux and LPBK which connects the output of the stereo
ADC to the input of the stereo DAC. LPBK provides a
mixed-mode analog – digital – analog loopback path be-
tween analog inputs and analog outputs.
BIT
Function
POP
PCM Out Path:
*0 = 3D allowed
1 = 3D bypassed
3D
National 3D Sound:
*0 = off
1= on
MIX
Mono output select:
*0 = Mix
1 = Mic
MS
Mic select:
*0 = MIC1
1 = MIC2
LPBK
ADC/DAC Loopback:
*0 = No Loopback
1 = Loopback
Default: 0000h
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC ’97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem
readiness and also to program the LM4550 powerdown
states. The 4 LSBs indicate status and the 8 MSBs control
powerdown.
The 4 LSBs of this register indicate the status of the 4 audio
subsections of the codec: Reference voltage, Analog mixers
and amplifiers, DAC section, ADC section. When the "Codec
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97
registers are in a fully operational state and that control and
status information can be transferred. It does not indicate
that the codec is ready to send or receive audio PCM data or
to pass signals through the analog I/O and mixers. To deter-
mine that readiness, the Controller must check that the 4
LSBs of this register are set to “1” indicating that the appro-
priate audio subsections are ready.
The powerdown bits PR0 – PR6 control internal subsections
of the codec. They are implemented in compliance with AC
’97 Rev 2.1 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
REF in addition to all the same mixer circuits as PR2. PR4
powers down the AC Link digital interface – see Figure 8 for
signal powerdown timing. PR5 disables internal clocks. PR6
powers down the Headphone amplifier. EAPD controls the
External Amplifier PowerDown bit.
BIT#
BIT
Function: Status
0
ADC
1 = ADC section ready to
transmit data
1
DAC
1 = DAC section ready to
accept data
2
ANL
1 = Analog mixers ready
3
REF
1 = V
REF is up to nominal level
BIT#
BIT
Function: Powerdown
8
PR0
1 = Powerdown ADCs and
Record Select Mux
9
PR1
1 = Powerdown DACs
10
PR2
1 = Powerdown Analog Mixer
(V
REF still on)
11
PR3
1 = Powerdown Analog Mixer
(V
REF off)
12
PR4
1 = Powerdown AC Link digital
interface (BIT_CLK off)
13
PR5
1 = Disable Internal Clock
14
PR6
1 = Powerdown Headphone
Amplifier
15
EAPD
External Amplifier PowerDown
*0 = Set EAPD Pin to 0 (pin 47)
Default: 000Xh
EXTENDED AUDIO ID REGISTER (28h)
This read-only (X201h) register identifies which AC ’97 Ex-
tended Audio features are supported. The LM4550 features
AMAP (Slot/DAC mappings based on Codec Identity), VRA
(Variable Rate Audio) and ID1, ID0, the Codec Identity bits
used to support multi-codec systems. AMAP is indicated by
a "1" in bit 9, VRA is indicated by a "1" in bit 0. The two
MSBs, ID1 and ID0, show the current Codec Identity as
defined by the Identity pins ID1#, ID0#. Note that the exter-
nal logic connections to ID1#, ID0# (pins 46 and 45) are
inverse in polarity to the value of the Codec Identity (ID1,
ID0) held in bits D15, D14. The AMAP Slot/DAC mappings
are given in Table 1 in the Multiple Codec section. Codec
mode selections are shown in the table below.
LM4550
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4550VHX | 制造商:Rochester Electronics LLC 功能描述:AC '97 REV 2.1 CODEC - Bulk |
| LM4550VHX/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP T/R |
| LM4558 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
| LM4558_08 | 制造商:HTC 制造商全稱:HTC Korea TAEJIN Technology Co. 功能描述:DUAL OPERATIONAL AMPLIFIERS |
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