AC Link Serial Interface Protocol
(Continued)
data from four slots in a given frame and so only checks the
valid-data bits for 4 slots. In Primary mode these tag bits are
for: slot 1 (Command Address), slot 2 (Command Data), slot
3 (PCM data for left DAC) and slot 4 (PCM data for right
DAC).
The last two bits in the Tag contain the Codec ID used to
select the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the control-
ler would not access a secondary codec unless it was pro-
viding valid Command Address and/or Data. When in one of
the secondary modes the LM4550 only checks the tag bits
for the Codec ID and for valid data in the two audio data
slots: slots3&4for Secondary mode 1, slots7&8for mode
2 and slots6&9for mode 3.
When sending an Output Frame to a Secondary mode co-
dec, a controller should set tag bits 14 and 13 to zero.
SLOT 0, OUTPUT FRAME
Bit
Description
Comment
15
Valid Frame
1 = Valid data in at least one
slot.
14
Control register
address
1 = Valid Control Address in
Slot 1 (Primary codec
only)
13
Control register
data
1 = Valid Control Data in Slot
2 (Primary codec only)
12
Left DAC data
in Slot 3
1 = Valid PCM Data in Slot 3
(Primary & Secondary 1
modes; Left Channel
audio)
11
Right DAC data
in Slot 4
1 = Valid PCM Data in Slot 4
(Primary & Secondary 1
modes; Right Channel
audio)
Bit
Description
Comment
10
Not Used
Controller should stuff this slot
with “0”s
9
Left DAC data
in Slot 6
1 = Valid PCM Data in Slot 6
(Secondary 3 mode;
Center Channel audio)
8
Left DAC data
in Slot 7
1 = Valid PCM Data in Slot 7
(Secondary 2 mode; Left
Surround Channel audio)
7
Right DAC data
in Slot 8
1 = Valid PCM Data in Slot 8
(Secondary 2 mode;
Right Surround Channel
audio)
6
Right DAC data
in Slot 9
1 = Valid PCM Data in Slot 9
(Secondary 3 mode; LFE
Channel audio)
5:2
Not Used
Controller should stuff these
slots with “0”s
1,0
Codec ID
(ID1, ID0)
the target codec in a
multi-codec system to receive
the control address and data
carried in the Output Frame
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4550 and whether the access
operation is a register read or register write. The MSB of slot
1 (bit 19) is set to 1 to indicate that the current access
operation is ’read’. Bits 18 through 12 are used to specify the
7-bit register address of the read or write operation. The
least significant twelve bits are reserved and should be
stuffed with zeros by the AC ’97 controller.
SLOT 1, OUTPUT FRAME
Bits
Description
Comment
19
Read/Write
1 = Read
0 = Write
18:12
Register
Address
Identifies the Status/Command
register for read/write
11:0
Reserved
Controller should set to "0"
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4550
when the access operation is ’write’. The least significant
four bits should be stuffed with zeros by the AC ’97 controller.
If the access operation is a register read, the entire slot, bits
19 through 0 should be stuffed with zeros.
SLOT 2, OUTPUT FRAME
Bits
Description
Comment
19:4
Control
Register Write
Data
Controller should stuff with
zeros if operation is “read”
3:0
Reserved
Set to "0"
10097205
FIGURE 5. Start of AC Link Output Frame
LM4550
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