參數(shù)資料
型號(hào)： LM4550VH/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 X 1.40 MM, LQFP-48
文件頁數(shù)： 15/30頁
文件大?。?/td> 611K
代理商： LM4550VH/NOPB
AC Link Serial Interface Protocol
(Continued)
SLOT 1, INPUT FRAME
Bits
Description
Comment
19
Reserved
Stuffed with "0" by LM4550
18:12
Status Register
Index
Echo of the requested Status
Register address.
11
Slot 3 Request
bit
(PCM Left
Audio)
0 = Controller should send
valid data in Slot 3 of the
next Output Frame.
1 = Controller should not
send Slot 3 data.
10
Slot 4 Request
bit
(PCM Right
Audio)
0 = Controller should send
valid data in Slot 4 of the
next Output Frame.
1 = Controller should not
send Slot 4 data.
9
Slot 5 Request
bit
Unused - set to "0" by LM4550
8
Slot 6 Request
bit
(PCM Center)
0 = Controller should send
valid data in Slot 6 of the
next Output Frame.
1 = Controller should not
send Slot 6 data.
7
Slot 7 Request
bit
(PCM Left
Surround)
0 = Controller should send
valid Slot 7 data in the
next Output Frame.
1 = Controller should not
send Slot 7 data.
6
Slot 8 Request
bit
(PCM Right
Surround)
0 = Controller should send
valid data in Slot 8 of
next Output Frame.
1 = Controller should not
send Slot 8 data.
5
Slot 9 Request
bit
(PCM LFE)
0 = Controller should send
valid data in Slot 9 of
next Output Frame.
1 = Controller should not
send Slot 9 data.
4:2
Unused Slot
Request bits
Stuffed with "0"s by LM4550
1,0
Reserved
Stuffed with "0"s by LM4550
SDATA_IN: Slot 2 – Status Data
This slot returns 16-bit status data read from a codec control/
status register. The codec sends the data in the frame fol-
lowing a read-request by the controller (bit 15, slot 1 of the
Output Frame). If no read-request was made in the previous
frame the codec will stuff this slot with zeros.
SLOT 2, INPUT FRAME
Bits
Description
Comment
19:4
Status Data
Data read from a codec
control/status register.
Stuffed with “0”s if no
read-request in previous frame.
3:0
Reserved
Stuffed with "0"s by LM4550
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain ampli-
fier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is
transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
SLOT 3, INPUT FRAME
Bits
Description
Comment
19:2
PCM Record
Left Channel
data
18-bit PCM audio sample from
left ADC
1:0
Reserved
Stuffed with "0"s by LM4550
SDATA_IN: Slot 4 – PCM Record Right Channel
This slot contains sampled data from the right channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain ampli-
fier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is
transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
SLOT 4, INPUT FRAME
Bits
Description
Comment
19:2
PCM Record
Right Channel
data
18-bit PCM audio sample from
right ADC
1:0
Reserved
Stuffed with "0"s by LM4550
SDATA_IN: Slots 5 to 12 – Reserved
Slots 5 – 12 of the AC Link Input Frame are not used for data
by the LM4550 and are always stuffed with zeros.
LM4550
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