參數(shù)資料
型號: LMK04002BEVAL
廠商: National Semiconductor
文件頁數(shù): 15/65頁
文件大?。?/td> 0K
描述: BOARD EVAL PRECISION CLOCK PLL
標準包裝: 1
系列: PowerWise®
主要目的: 計時,時鐘調(diào)節(jié)器
嵌入式:
已用 IC / 零件: LMK04002
主要屬性: 122.88 MHz VCXO
次要屬性: 集成式 PLL 和 VCO
已供物品: 板,線纜
產(chǎn)品目錄頁面: 1275 (CN2011-ZH PDF)
100
1000
10000
100000
OFFSET (Hz)
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
d
Bc
1000000
10000000
100000000
100
1000
10000
100000
OFFSET (Hz)
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
d
Bc
1000000
10000000
100000000
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Typical Performance Characteristics (continued)
The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor,
due to the distribution section accounting for the delay noise, can be calculated as: Total Output Noise = 10 x
log(10Output Buffer Noise/10 + 10Delay Noise Floor/10).
Typical LVDS Phase Noise, FCLK = 250 MHz, RMS Jitter = 192 fs (100 Hz to 20 MHz)
Figure 8.
Typical LVPECL Phase Noise, FCLK = 250 MHz, RMS Jitter = 196 fs (100 Hz to 20 MHz)
Figure 9.
Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 A, PLL1 Loop BW = 20 Hz, VCXO
= 100 MHz Crystek CVPD-920-100, PLL2_R = 2, PLL2_N = 10, PLL2_CP_GAIN = 1600 A, PLL2 Loop BW = 137
kHz, fVCO = 1500 MHz, VCO_DIV = 3, CLKoutX_DIV = 2, CLK_DLY = OFF.
22
Copyright 2008–2011, Texas Instruments Incorporated
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