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參數(shù)資料
| 型號(hào)： | LMK04002BEVAL |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 20/65頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL PRECISION CLOCK PLL |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04002 |
| 主要屬性： | 122.88 MHz VCXO |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜 |
| 產(chǎn)品目錄頁(yè)面： | 1275 (CN2011-ZH PDF) |
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tCES
tCS
D27
D26
D25
D24
tCH
tCWH
tCWL
D23
D0
A3
A2
A1
A0
MSB
LSB
DATAuWire
CLKuWire
LEuWire
tES
tEWH
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Fout
The buffered output of the internal VCO is available at the Fout pin. This is a single-ended output (sinusoid).
Each time the PLL2_N counter value is updated via the uWire interface, an internal algorithm is triggered that
optimizes the VCO performance.
Digital Lock Detect 1 Bypass
The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate
the internal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must achieve lock status. A
digital lock detect is used in PLL1 to monitor its lock status. After lock is achieved by PLL1, the coarse tuning
circuitry is enabled and frequency calibration for the internal VCO begins.
The (DLD_BYP) pin is provided to allow an external bypass cap to be connected to the digital lock detect 1. This
capacitor will eliminate potential glitches at initial startup of PLL1 due to unknown phase relationships between
the Ncntr1 and Rcntr1.
Bias
Proper bypassing of this pin by a 1 F capacitor connected to VCC is important for low noise performance.
General Programming Information
LMK040xx devices are programmed using several 32-bit registers. Each register consists of a 4-bit address field
and 28-bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data field is formed by bits 4
through 31 (MSBs). The contents of each register are clocked in MSB first (bit 31), and the LSB (bit 0) last.
During programming, the LE signal should be held LOW. The serial data is clocked in on the rising edge of the
CLK signal. After the LSB (bit 0) is clocked in the LE signal should be toggled LOW-to-HIGH-to-LOW to latch the
contents into the register selected in the address field. Registers R0-R4, R7, and R8-R15 must be programmed
in order to achieve proper device operation. Figure 12 illustrates the serial data timing sequence.
Figure 12. uWire Timing Diagram
To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming
Register 15. Changes to PLL2_R Counter or the OSCin port signal require Register 15 to be reloaded in order to
activate the frequency calibration process.
Recommended Programming Sequence
The recommended programming sequence involves programming R7 with the reset bit set to 1 (Reg. 7, bit 4) to
ensure the device is in a default state. If R7 is programmed again, the reset bit should be set to 0. Registers are
programmed in order with R15 being the last register programmed. An example programming sequence is
shown below:
Program R7 with the RESET bit = 1 (b4 = 1). This ensures that the device is configured with default settings.
When RESET = 1, all other R7 bits are ignored.
–
- If R7 is programmed again during the initial configuration of the device, the RESET bit should be cleared
(b4 = 0)
Program R0 through R4 as necessary to configure the clock outputs as desired. These registers configure
clock channel functions such as the channel multiplexer output selection, divide value, delay value, and
enable/disable bit.
Copyright 2008–2011, Texas Instruments Incorporated
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| LMK04002BEVAL/NOPB | 功能描述:BOARD EVAL FOR LMK04002B RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:PowerWise® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:數(shù)字電位器 嵌入式:- 已用 IC / 零件:AD5258 主要屬性:- 次要屬性:- 已供物品:板 相關(guān)產(chǎn)品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
| LMK04002BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04002BISQ/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04002BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R |
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