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| 型號： | LMK04002BEVAL |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 41/65頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL PRECISION CLOCK PLL |
| 標準包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計時，時鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04002 |
| 主要屬性： | 122.88 MHz VCXO |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 1275 (CN2011-ZH PDF) |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Table 33. Typical Current Consumption for Selected Functional Blocks (continued)
Power
Typical ICC
Power
Dissipated in
(Temp = 25 °C,
Dissipated in
LVPECL/2VPECL
Block
Condition
VCC = 3.3 V)
device
Emitter
(mA)
(mW)
Resistors
(mW)
LVPECL/2VPECL buffer (enabled and with 120
Ω emitter
40
82
50
resistors)
LVPECL/2VPECL
LVPECL/2VPECL buffer (disabled and with 120
Ω emitter
Buffer
21.7
47
25
resistors)
LVPECL/2VPECL (disabled and with no emitter resistors)
0
-
LVCMOS buffer static ICC, CL = 5 pF
4.5
15
-
LVCMOS Buffer
LVCMOS buffer dynamic ICC, CL = 5 pF, CLKout = 100
(1)
16
53
-
MHz
Entire device
LMK0400x (2) (3)
379.5
1102
150
(Single input clock
LMK0401x (2) (3)
377.5
996
250
(CLKIN_SEL = 0
LMK0403x (2) (3)
or 1); LOS
disabled; PLL1
and PLL2 locked;
Fout disabled; All
337.1
1012
100
CLKouts are on;
No delay); Divide
> 2 on each
output.
(1)
Dynamic power dissipation of LVCMOS buffer varies with output frequency and can be found in the LVCMOS dynamic ICC vs frequency
plot, as shown in Typical Performance Characteristics. Total power dissipation of the LVCMOS buffer is the sum of static and dynamic
power dissipation. CLKoutXa and CLKoutXb are each considered an LVCMOS buffer.
(2)
Assuming ThetaJ = 27.4 °C/W, the total power dissipated on chip must be less than 40/27.4 = 1450 mW to guarantee a junction
temperature is less than 125 °C.
(3)
Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.2.
Current Consumption / Power Dissipation Calculations
Due to the myriad of possible configurations the following table serves to provide enough information to allow the
user to calculate estimated current consumption of the device. Unless otherwise noted VCC = 3.3 V, TA = 25 °C.
From Table 33 the current consumption can be calculated in any configuration. For example, the current for the
entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output in bypassed mode can be calculated by
adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL
output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from
the current draw is dissipated in the external 120
Ω resistors which doesn't add to the power dissipation budget
for the device. If delays or divides are switched in, then the additional current for these stages needs to be added
as well.
For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device
minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter
resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS
(CLKout0) & 1 LVPECL (CLKout1) operating at 3.3 V, we calculate 3.3 V × (115 + 10 + 10 + 19.3 + 40) mA = 3.3
V × 194.3 mA = 641.2 mW. Because the LVPECL output (CLKout1) has the emitter resistors hooked up and the
power dissipated by these resistors is 50 mW, the total device power dissipation is 641.2 mW - 50 mW = 591.2
mW.
When the LVPECL output is active, ~1.7 V is the average voltage on each output as calculated from the LVPECL
VOH & VOL typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.7 V)
2 /
120
Ω = 25 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the
power dissipated in each emitter resistor is approximately (1.07 V)2 / 120
Ω = 9.5 mW.
46
Copyright 2008–2011, Texas Instruments Incorporated
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