參數(shù)資料
型號： LMK04002BEVAL
廠商： National Semiconductor
文件頁數(shù)： 64/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PRECISION CLOCK PLL
標準包裝： 1
系列： PowerWise®
主要目的： 計時，時鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04002
主要屬性： 122.88 MHz VCXO
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCPout1=VCC/2, PLL1_CP_GAIN
-25
= 100b
VCPout1=VCC/2, PLL1_CP_GAIN
-50
= 101b
VCPout1=VCC/2, PLL1_CP_GAIN
-100
= 110b
VCPout1=VCC/2, PLL1_CP_GAIN
PLL1 Charge Pump Sink
-400
ICPout1 SINK
A
= 111b
Current (5)
PLL1_CP_GAIN = 000b
NA
PLL1_CP_GAIN = 001b
NA
VCPout1=VCC/2, PLL1_CP_GAIN
-20
= 010b
VCPout1=VCC/2, PLL1_CP_GAIN
-80
= 011b
Charge Pump Sink / Source
ICPout1 %MIS
VCPout1 = VCC/2, T = 25 °C
3
10
%
Mismatch
Magnitude of Charge Pump
0.5 V < VCPout1 < VCC - 0.5 V
ICPout1VTUNE
Current vs. Charge Pump
4
%
TA = 25 °C
Voltage Variation
Charge Pump Current vs.
ICPout1 %TEMP
4
%
Temperature Variation
Charge Pump TRI-STATE
PLL1 ICPout1 TRI
0.5 V < VCPout < VCC - 0.5 V
5
nA
Leakage Current
PLL2 Reference Input (OSCin) Specifications
EN_PLL2_REF 2X = 0
250
PLL2 Reference Input
(7)
fOSCin
MHz
(6)
EN_PLL2_REF 2X = 1
50
PLL2 Reference Clock
SLEWOSCin
20% to 80%
0.15
0.5
V/ns
minimum slew rate on OSCin
AC coupled; Single-ended
Input Voltage for OSCin or
VOSCin (Single-ended)
(Unused pin AC coupled to
0.2
2.0
Vpp
OSCin*
GND)
VOSCin (Differential)
Differential voltage swing
AC coupled
0.4
3.1
Vpp
Crystal Oscillator Mode Specifications
fXTAL
Crystal Frequency Range
6
20
MHz
Crystal Effective Series
ESR
6 MHz < FXTAL < 20 MHz
100
Ohms
Resistance
Vectron VXB1 crystal, 12.288
PXTAL
Crystal Power Dissipation (8)
200
W
MHz, RESR < 40 Ω
Input Capacitance of
CIN
-40 to +85 °C
6
pF
LMK040xx OSCin port
PLL2 Phase Detector and Charge Pump Specifications
fPD
Phase Detector Frequency
100
MHz
(6)
FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
(7)
The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
(8)
See Application Section discussion of Crystal Power Dissipation.
8
Copyright 2008–2011, Texas Instruments Incorporated
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