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參數(shù)資料
| 型號： | LP1072 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 802.11a/b/g Baseband System Solution |
| 中文描述： | 802.11a/b/g無線基帶系統(tǒng)解決方案 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LP1072 |
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LP1072 Advance Information, Rev. 0.3
16
Freescale Semiconductor
PRELIMINARY
Timers/Reset
5
Timers/Reset
The TCXO generates the 40MHz RFIC 800 mV clipped sine wave reference clock.
The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO
reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL
synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM,
PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the
TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock.
The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock
reference to be driven by an external signal.
Figure 3
illustrates the high level clocking of the LP1072 with the associated pins.
Figure 3. LP1072 Clocks
5.1
System Clock
The LP1072 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal
oscillator (TCXO) running at 40MHz with a frequency resolution of
±
20 ppm or better.
5.2
PLL Block
PLL Bypass
5.3
Low Frequency Clock
The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
TCXO
Clock
Control
Cuircuits
40 MHz
44 MHz
20 MHz
22 MHz
PLL
40 MHz
PLL_BYPAS
S
TCXO_BYPASS
TCXO_BYPASS_CLK
PLL_BYPASS_CLK
XTAL
32 kHz
XTAL_BYPASS
XTAL_BYPASS_CLK
88 MHz
32 kHz
ARM
AFE
Chip
Boundary
FAST_CLK_PWR
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