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參數(shù)資料
| 型號： | LP1072 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 802.11a/b/g Baseband System Solution |
| 中文描述： | 802.11a/b/g無線基帶系統(tǒng)解決方案 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LP1072 |
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LP1072 Advance Information, Rev. 0.3
4
Freescale Semiconductor
PRELIMINARY
Functional Description
3
Functional Description
Figure 1
is a functional block diagram of the LP1072.
Figure 1. Functional Block Diagram
3.1
Embedded Processor Subsystem
The embedded Processor Subsystem consists of the following:
An embedded ARM7TDMI microprocessor running at 88 MHz
An ARM Peripheral Subsystem accessed via an extended APB (APB+) bus
Packaging Options
200-pin VFBGA, 13.0 x 13.0 x 1.0(max) mm
Semiconductor Technology
0.18 micron
RF Support
Maxim, Airoha
Certification
Wi-Fi (incl. WPA), WQHL, FCC Part 15
Table 1. Specifications (continued)
Feature
Details
A
ARM7TDMI
Bridge
Interrupt
Controller
SDIO
Registers
UART
JTAG
EEPROM
Interface
GPIO
Memory
Controller
On-Chip
RAM/ROM
ARM
Subsystem
Clock
Control
A
WBSP
TM
PLL
Watchdog
Timer
I/Q ADC
I/Q DAC
Aux ADC
Aux DAC
RSSI
ADC
AFE
ARM
Interface
AFE
Control
MAC-PHY
Interface
Clock Select
Logic
WEP
Engine
AES
Engine
Shared
Memory
Controller
Shared
Memory
ARM
Interface
AHB
AHB
Generic
Host
Interface
DMA
MAC Subsystem
PHY
Subsystem
Host
Interface
Protocol
Accelerator
Subsystem
RMB
Registers
Clock
Gating
802.11
Protocol
Accelerator
LP1072 Chip Boundary
CLKIN
(From TCXO)
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