參數(shù)資料
型號： LPC2939FBD208
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208
文件頁數(shù)： 20/99頁
文件大?。?/td> 1945K
代理商： LPC2939FBD208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
20 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.7.2
Base clock and branch clock relationship
Table 7
contains an overview of all the base blocks in the LPC2939 and their derived
branch clocks. A short description is given of the hardware parts that are clocked with the
individual branch clocks. In relevant cases more detailed information can be found in the
specific subsystem description. Some branch clocks have special protection since they
clock vital system parts of the device and should not be switched off. See
Section 6.16.5
for more details of how to control the individual branch clocks.
Table 7.
Base clock
CGU0 base clock and branch clock overview
Branch clock name
Parts of the device clocked by this
branch clock
watchdog timer
ARM968E-S and TCMs
AHB bus infrastructure
AHB side of bridge in PCRSS
flash memory controller
embedded SRAM controller 0 (32 kB)
embedded SRAM controller 1 (16 kB)
external Static Memory Controller
(SMC)
General SubSystem (GESS)
Vectored Interrupt Controller (VIC)
Peripheral SubSystem (PESS)
GPIO bank 0
GPIO bank 1
GPIO bank 2
GPIO bank 3
GPIO bank 4
GPIO bank 5
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
GPDMA
USB registers
PCRSS, CGU, RGU and PMU logic
clock
APB side of the IVNSS
CAN controller Acceptance Filter
CAN channel 0
CAN channel 1
I
2
C0
I
2
C1
LIN channel 0
LIN channel 1
BASE_SAFE_CLK
BASE_SYS_CLK
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
[1]
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_GPIO4
CLK_SYS_GPIO5
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_SYS_USB
CLK_PCR_SLOW
[2]
[4]
BASE_PCR_CLK
[1]
[3]
BASE_IVNSS_CLK
CLK_IVNSS_APB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
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