參數(shù)資料
型號(hào)： LPC2939FBD208
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208
文件頁數(shù)： 57/99頁
文件大?。?/td> 1945K
代理商： LPC2939FBD208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
57 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.16.3
Clock generation for USB (CGU1)
The CGU1 block is functionally identical to the CGU0 block and generates two clocks for
the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and
fractional divider. The PLLs used in CGU0 and CGU1 are identical (see
Section 6.16.2.2
).
The clock input to the CGU1 PLL is provided by one of two base clocks generated in the
CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL
can be configured to drive the output clock directly.
6.16.3.1
Pin description
The CGU1 module in the LPC2939 has the pins listed in
Table 28
below.
Table 29.
Symbol
CLK_OUT
6.16.4
Reset Generation Unit (RGU)
The RGU controls all internal resets.
The key features of the Reset Generation Unit (RGU) are:
Reset controlled individually per subsystem
Automatic reset stretching and release
Fig 15. Block diagram of the CGU1
PLL
FDIV0
OUT 0
OUT 2
002aae148
clkout
clkout120
clkout240
CLOCK GENERATION UNIT
(CGU1)
AHB TO DTL BRIDGE
BASE_USB_CLK
BASE_OUT_CLK
OUT 1
BASE_USB_I2C_CLK
BASE_ICLK1_CLK
BASE_ICLK0_CLK
CGU1 pins
Direction
OUT
Description
clock output
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