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| 型號(hào)： | LPC2939FBD208 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208 |
| 文件頁(yè)數(shù)： | 45/99頁(yè) |
| 文件大?。?/td> | 1945K |
| 代理商： | LPC2939FBD208 |
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LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
45 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Table 23.
Symbol
ADC0 IN[7:0]
[1]
VREFP, VREFN, V
DDA(ADC3V3)
must be connected for the 5 V ADC0 to operate properly.
The analog inputs of ADC0 are internally multiplied by a factor of 3.3 / 5. If V
DDA(ADC5V0)
is connected to
3.3 V, the maximum digital result is 1024
3.3 / 5.
[2]
[3]
V
DDA(ADC5V0)
and V
DDA(ADC3V3)
must be set as follows: V
DDA(ADC5V0)
= V
DDA(ADC3V3)
1.5.
Remark:
The following formula only applies to ADC0:
Voltage variations on VREFP (i.e. those that deviate from voltage variations on the
V
DDA(ADC5V5)
pin) are visible as variations in the measurement result.
Equation 3
shows
the formula used to determine the conversion result of an input voltage V
IN
on ADC0:
(3)
Remark:
Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see
Table 34
) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant. The
ADC0 pins are 5 V tolerant.
6.15.4.3
Clock description
The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and
CLK_ADCx (x = 0, 1, or 2), see
Section 6.7.2
. Note that each ADC has its own
CLK_ADCx and CLK_MSCSS_ADCx_APB branch clocks for power management. If an
ADC is unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off.
The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to
CLK_MSCSS_APB since they are derived from the same base clock
BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical
since they are derived from the same base clock BASE_ADC_CLK.
The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.
Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also
Figure 9
.
6.15.5
Pulse Width Modulator (PWM)
The MSCSS in the LPC2939 includes four PWM modules with the following features.
Analog to digital converter pins
Pin name
IN0[7:0]
Direction Description
IN
analog input for 5.0 V ADC0, channel 7 to
channel 0
IN
analog input for 3.3 V ADC1/2, channel 7 to
channel 0
IN
ADC external start-trigger input (n is 0, 1, or 2)
IN
ADC LOW reference level
IN
ADC HIGH reference level
V
DDA(ADC5V0)
[1]
IN
5 V high-power supply and HIGH reference for
ADC0. Connect to clean 5 V as HIGH reference.
May also be connected to 3.3 V if 3.3 V
measurement range for ADC0 is needed.
[2][3]
V
DDA(ADC3V3)
IN
ADC1 and ADC2 3.3 V supply (also used for
ADC0).
[3]
ADC1/2 IN[7:0]
IN1/2[7:0]
ADCn_EXTSTART
VREFN
VREFP
V
DDA(ADC5V0)
CAP1[n]
VREFN
VREFP
V
DDA(ADC3V3)
2
3
--
V
IN
1
2
--
V
DDA ADC5V0
–
1
2
--
V
DDA ADC3V3
+
–
V
VREFP
V
VREFN
-------------------------------------------
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