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參數(shù)資料
| 型號(hào)： | M12S128168A-10TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, TSOP2-54 |
| 文件頁(yè)數(shù)： | 5/44頁(yè) |
| 文件大?。?/td> | 967K |
| 代理商： | M12S128168A-10TG |
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ES MT
M12S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
Nov. 2006
5/44
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0
C
°
~ 70
C
°
)
CAS
Latency
Version
-10
Parameter
Symbol
Test Condition
Unit Note
Operating Current
(One Bank Active)
I
CC1
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
60
mA
1
I
CC2P
CKE
≤
V
IL
(max), t
CC
=10ns
2
mA
Precharge Standby
Current in power-down
mode
I
CC2PS
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
2
mA
I
CC2N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=10ns
Input signals are changed one time during 20ns
15
mA
Precharge Standby
Current in non
power-down mode
I
CC2NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
9
mA
I
CC3P
CKE
≤
V
IL
(max), t
CC
=10ns
6
Active Standby Current
in power-down mode
I
CC3PS
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
6
mA
I
CC3N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=10ns
Input signals are changed one time during 20ns
20
mA
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
20
mA
Operating Current
(Burst Mode)
Refresh Current
I
CC4
I
OL
= 0Ma, Page Burst
All Band Activated, t
CCD
= t
CCD (min)
80
mA
1
I
CC5
t
RC
≥
t
RC
(min), t
CC
=10ns
180
mA
2
Self Refresh Current
I
CC6
CKE
≤
0.2V
2
mA
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC(min)
.
2. Refresh period is 64ms. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any
given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO
REFRESH command is 8x15.6
μ
s.). Addresses are changed only one time during t
CC(min)
.
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PDF描述 |
|---|---|
| M12S16161A-7BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-7TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S64322A | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12S128168A-6BG | 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S128168A-6TG | 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S128168A-7BG | 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S128168A-7TG | 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S128324A | 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
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