參數(shù)資料
型號(hào)： M12S128168A-10TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, TSOP2-54
文件頁(yè)數(shù)： 8/44頁(yè)
文件大小： 967K
代理商： M12S128168A-10TG
ES MT
M12S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
Nov. 2006
8/44
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1
CKEn
CS RAS
CAS
WE
DQM
BA0
BA1
A10/AP
A11
A9~A0
Note
Mode Register set
Extended Mode Register
Set
Auto Refresh
H
X
L
L
L
L
X
OP CODE
1,2
Register
H
X
L
L
L
L
X
OP CODE
1,2
H
L
3
3
3
3
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
Refresh
Self
Refresh
Exit
L
H
X
Bank Active & Row Addr.
H
X
V
Row Address
Auto Precharge Disable
L
4
Read &
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
H
Column
Address
(A0~A8)
Column
Address
(A0~A8)
4,5
Auto Precharge Disable
L
4
Write &
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
H
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Bank Selection
V
L
Precharge
All Banks
H
X
L
L
H
L
X
X
H
X
H
X
X
X
Entry
H
L
L
X
H
L
H
L
H
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
No Operating Command
H
H
V
X
X
X
7
X
Entry
Exit
H
L
L
H
L
X
H
X
H
X
L
X
X
X
Deep Power Down Mode
X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If BA0 and BA1 are “Low” at read ,write , row active and precharge ,bank A is selected.
If BA0 is “Low” and BA1 is “High” at read ,write , row active and precharge ,bank B is selected.
If BA0 is “High” and BA1 is “Low” at read ,write , row active and precharge ,bank C is selected.
If BA0 and BA1 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
相關(guān)PDF資料
PDF描述
M12S16161A-7BG 512K x 16Bit x 2Banks Synchronous DRAM
M12S16161A-7TG 512K x 16Bit x 2Banks Synchronous DRAM
M12S64322A 512K x 32 Bit x 4 Banks Synchronous DRAM
M12S64322A-6BG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12S64322A-6TG 512K x 32 Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12S128168A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M12S128168A-6TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M12S128168A-7BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M12S128168A-7TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M12S128324A 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*