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參數(shù)資料
| 型號： | M12S16161A-7TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50 |
| 封裝： | 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大?。?/td> | 628K |
| 代理商： | M12S16161A-7TG |
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ES MT
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
M12S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.1
21/29
*Note:
1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
C L O C K
C K E
A D D R
DQ
DQ M
A10/AP
BA
RAa
CAa
CAb
RAa
QAa0 QAa1
QAb1
QAb0
QAb2
*Note1
Row Active
(A-Bank)
Read
(A- Bank)
Burst Stop
Read
(A- Bank)
:Don't Care
HIGH
CL=2
CL=3
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
QAa0 QAa1
QAb1
QAb0
QAb2
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
1
1
2
2
Precharge
(A- Bank)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CS
RAS
CAS
WE
*Note2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12S16161A-7TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
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| M12S64164A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
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