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參數(shù)資料
| 型號： | M25PE80-VMP6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 599K |
| 代理商： | M25PE80-VMP6T |
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M25PE80
struction) is executed. The device consumption
drops further to I
CC2
. When in this mode, only the
Release from Deep Power-down instruction is ac-
cepted. All other instructions are ignored. The de-
vice remains in the Deep Power-down mode until
the Release from Deep Power-down instruction is
executed. This can be used as an extra software
protection mechanism, when the device is not in
active use, to protect the device from inadvertent
Write, Program or Erase instructions.
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit.
The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
WEL bit.
The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
Table 2. Status Register Format
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25PE80 features
the following data protection mechanisms:
Power On Reset and an internal timer (t
PUW
)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Reset (RESET) driven Low
–
Write Disable (WRDI) instruction
completion
–
Page Write (PW) instruction completion
■
■
■
–
–
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction
completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
The Hardware Protected mode is entered
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use.
The Software Protection is managed by
specific Lock Registers assigned to each
sector and sub-sector as follows:
–
each 64KB sector has a Lock Register
–
inside sector 0 and sector 15, each 4KB
sub-sector also has a Lock Register (in
addition to the Lock Register at sector
level)
The Lock Registers can be read and written
using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the
protection of each sector/sub-sector: the Write
Lock Bit and the Lock Down Bit.
–
Write Lock Bit:
The Write Lock Bit determines whether
the contents of the sector/sub-sector can
be modified (using the Write, Program or
Erase instructions). When the Write Lock
Bit is set, ‘1’, the sector/sub-sector is write
protected – any operations that attempt to
change the data in the sector/sub-sector
will fail. When the Write Lock Bit is reset to
‘0’, the sector/sub-sector is not write
protected by the Lock Register, and may
be modified, unless TSL is Low (in which
case the top sector will remain write
protected).
–
Lock Down Bit:
The Lock Down Bit provides a mechanism
for protecting software data from simple
hacking and malicious attack. When the
Lock Down Bit is set, ‘1’, further
–
–
–
■
■
■
■
b7
b0
0
0
0
0
0
0
WEL WIP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE80-VMP6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMP6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMP6 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMW6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE80-VMP6TG | 功能描述:閃存 SERIAL PAGE ERASE FLASH 8 Mbit Datas RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M25PE80-VMP6TP | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE80-VMS6G | 制造商:Micron Technology Inc 功能描述:NOR Flash Serial-SPI 3.3V 8Mbit 1M x 8bit 8ns 8-Pin QFN Tray |
| M25PE80-VMS6P | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE80-VMS6TG | 功能描述:IC FLASH 8MBIT 75MHZ 8QFN RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Forté™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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