參數(shù)資料
型號： M29F105B
廠商： 意法半導體
英文描述： 1Mbit (64Kb x16, Block Erase) Single Supply Flash Memory(1Mb閃速存儲器)
中文描述： 為1Mbit（64Kb的x16插槽，塊擦除）單電源閃存存儲器（1MB閃速存儲器）
文件頁數(shù)： 11/28頁
文件大小： 200K
代理商： M29F105B
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
1
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±
1
μ
A
I
CC1
Supply Current (Read) TTL
E = V
IL
, G = V
IH
, f = 6MHz
50
mA
I
CC2
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC3
Supply Current (Standby) CMOS
E = V
CC
±
0.2V
100
μ
A
I
CC4
Supply Current (Program or Erase)
Byte program, Block or
Chip Erase in progress
20
mA
V
IL
Input Low Voltage
–0.5
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8mA
0.45
V
V
OH
Output High VoltageTTL
I
OH
= –2.5mA
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
V
CC
–0.4V
V
I
OH
= –2.5mA
0.85 V
CC
V
V
ID
A9, E, G Voltage
11.5
12.5
V
I
ID
A9, E, G Current
A9 = V
ID
100
μ
A
V
LKO
Supply Voltage(Erase and
Program lock-out)
3.2
4.2
V
Table13. DC Characteristics
(T
A
= 0 to 70
°
C or –40 to85
°
C; V
CC
= 5V
±
10%)
mands and block addresses can be written sub-
sequentlyto eraseother blocksin parallel, without
further Coded cycles. The erase will start after an
erase timeout period of 80
μ
s. Thus, additional
EraseConfirmcommandsforotherblocksmustbe
given within this delay.
The input of a new Erase Confirm command will
restartthetimeoutperiod.Thestatusof theinternal
timercan be monitoredthroughthe levelof DQ3,if
DQ3 is ’0’ the Block Erase Command has been
given and the timeout is running, if DQ3 is ’1’, the
timeout has expired and the P/E.C. is erasing the
Block(s). If the second command given is not an
eraseconfirmorif theCodedcyclesarewrong,the
instructionaborts, and the deviceis resetto Read
Array.It is notnecessaryto programtheblockwith
0000h as the P/E.C. will do this automaticallybe-
foreto erasingto FFFFh.Readoperationsafterthe
sixthrisingedgeofWorEoutputthestatusregister
statusbits.
Duringtheexecutionof theerasebytheP/E.C.,the
memory accepts onlythe Erase SuspendES and
Read/Reset RD instructions.Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggleduring the erase operation.They stop
when erase is completed. After completion the
StatusRegisterbitDQ5returns’1’iftherehasbeen
an erase failure. In such a situation,the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/ResetRD instructionis necessaryin orderto
reset the P/E.C.
11/28
M29F105B
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