參數(shù)資料
型號: M29F105B
廠商: 意法半導體
英文描述: 1Mbit (64Kb x16, Block Erase) Single Supply Flash Memory(1Mb閃速存儲器)
中文描述: 為1Mbit(64Kb的x16插槽,塊擦除)單電源閃存存儲器(1MB閃速存儲器)
文件頁數(shù): 12/28頁
文件大小: 200K
代理商: M29F105B
Symbol
Alt
Parameter
TestCondition
M29F105B
Unit
-55
-70
-90
V
CC
= 5V
±
5%
V
CC
= 5V
±
10%
High Speed
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
t
AVAV
t
RC
Address Validto Next
Address Valid
E = V
IL
, G = V
IL
55
70
90
ns
t
AVQV
t
ACC
Address Validto
Output Valid
E = V
IL
, G = V
IL
55
70
90
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to
Output Transition
G = V
IL
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to
Output Valid
G = V
IL
55
70
90
ns
t
GLQX(1)
t
OLZ
Output EnableLow to
Output Transition
E = V
IL
0
0
ns
t
GLQV(2)
t
OE
Output EnableLow to
Output Valid
E = V
IL
20
30
35
ns
t
EHQX
t
OH
Chip Enable High to
Output Transition
G = V
IL
0
0
ns
t
EHQZ(1)
t
HZ
Chip Enable High to
Output Hi-Z
G = V
IL
15
20
20
ns
t
GHQX
t
OH
Output EnableHigh to
Output Transition
E = V
IL
0
0
ns
t
GHQZ
(1)
t
DF
Output EnableHigh to
Output Hi-Z
E = V
IL
15
20
20
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
ns
Notes:
1. Sampled only,not 100% tested.
2. G may be delayed by up to t
ELQV
- t
GLQV
afterthe falling edge of E withoutincreasing t
ELQV
.
Table14. ReadAC Characteristics
(T
A
= 0 to 70
°
C or –40 to85
°
C)
ChipErase(CE)Instruction.
Thisinstructionuses
six write cycles.The Set-up command80h iswrit-
tento address555h on thethirdcycleafterthe two
Codedcycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after
anothertwo Codedcycles.Ifthe secondcommand
givenis notaneraseconfirmor if theCodedcycles
are wrong, the instruction abortsand thedevice is
resetto ReadArray. It is not necessaryto program
the array with 0000h first as the P/E.C. will auto-
matically do this before erasing it to FFFFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tionof theerasebytheP/E.C.,DataPollingbit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stopwheneraseiscompleted.Aftercompletionthe
StatusRegisterbitDQ5returns’1’iftherehas been
an Erase Failure.
12/28
M29F105B
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