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參數(shù)資料
| 型號： | M29F105B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1Mbit (64Kb x16, Block Erase) Single Supply Flash Memory(1Mb閃速存儲器) |
| 中文描述： | 為1Mbit（64Kb的x16插槽，塊擦除）單電源閃存存儲器（1MB閃速存儲器） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 200K |
| 代理商： | M29F105B |
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Block Protection.
Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
eraseoperations.Thismodeis activatedwhenboth
A9 and G are raised to V
ID
and an address in the
block is appliedon A12-A15.The Block Protection
algorithmis showninFigure14. Blockprotectionis
initiated on the edge of W falling to V
IL
. Thenafter
a delayof 100
μ
s, the edge of W rising to V
IH
ends
theprotectionoperations.Blockprotectionverifyis
achievedby bringingG, E, A0andA6to V
IL
andA1
to V
IH
, whileWis at V
IH
andA9 atV
ID
. Underthese
conditions,readingthe data outputwill yield 01h if
the block defined by the inputs on A12-A15 is
protected.Any attempt to programor erase a pro-
tected block will be ignored by the device. The
blockscanalsobeprotectedwithouttheuseof V
ID
,
by giving to the memory the instruction BP (see
Table9).
Block Unprotection.
All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protectedbeforethe unprotectionoperation.Block
unprotectionis activatedwhen A9, G and E are at
V
ID
and A12, A15 at V
IH
. The Block Unprotection
algorithm is shown in Figure 15. Unprotection is
initiatedby theedgeof WfallingtoV
IL
. Afteradelay
of 10ms, the unprotectionoperation will end. Un-
protectionverifyis achievedby bringingGandE to
V
IL
whileA0 is at V
IL
, A6 and A1 areat V
IH
andA9
remains at V
ID
. In these conditions, reading the
outputdatawill yield 00hif theblockdefinedby the
inputsA12-A15hasbeensuccesfullyunprotected.
Eachblockmustbeseparatelyverifiedbygivingits
address in orderto ensurethat it has been unpro-
tected.The blockscan alsobeunprotectedwithout
theuse of V
ID
, by givingto thememorythe instruc-
tion BU (seeTable 9).
INSTRUCTIONSAND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, ReadElectronicSignature,Read BlockPro-
tection,Program, BlockProtect,BlocksUnprotect,
Block Erase, Chip Erase, Erase Suspend and
Erase Resume. Commands are made of address
anddatasequences.The instructionsrequirefrom
1 to 6 cycles, the first or first three of which are
alwayswrite operationsusedto initiatethe instruc-
tion.Theyarefollowedbyeitherfurtherwritecycles
to confirm the first command or execute the com-
mandimmediately.Commandsequencingmustbe
followed exactly. Any invalid combination of com-
mands will reset the device to Read Array. The
increased number of cycles has been chosen to
assure maximum data security. Instructions are
initialised by two initial Codedcycles which unlock
the Command Interface. In addition, for Erase,
instruction confirmation is again preceded by the
two Coded cycles.
Status RegisterBits
P/E.C.statusis indicatedduringexecutionbyData
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwill automaticallyoutputthesefive
StatusRegisterbits.The P/E.C.automaticallysets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables8 and 10.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
DuringErase operation,it outputsa ’0’.After com-
pletionof the operation,DQ7will outputthe bit last
programmedor a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourthW pulse for programmingor
after the sixth W pulse for erase. It must be per-
formedat theaddress being programmedor at an
address within the block being erased. If all the
blocksselectedfor erasureare protected,DQ7will
be setto ’0’for about100
μ
s, andthenreturn to the
previous addressed memory data value. See Fig-
ure11for the Data Pollingflowchartand Figure10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeingerasedandthedatavalueon other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the samebehaviour as
in the normal program execution outside of the
suspendmode.
ToggleBit (DQ6).
WhenProgrammingor Erasing
operationsarein progress,successiveattemptsto
readDQ6willoutputcomplementarydata. DQ6will
toggle following toggling of either G, or E when G
is low. Theoperationis completed when two suc-
cessivereadsyieldthesameoutputdata.The next
readwilloutputthebitlastprogrammedora’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations,that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100
μ
s and then
returnback to Read.DQ6willbe setto ’1’if aRead
6/28
M29F105B
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