參數(shù)資料
型號(hào)： M29W800T100M1R
廠商： 意法半導(dǎo)體
英文描述： Low-Power Configurable Multiple-Function Gate 6-SOT -40 to 85
中文描述： 8兆1兆x8或512KB的x16插槽，引導(dǎo)塊低壓?jiǎn)坞娫撮W存
文件頁(yè)數(shù)： 11/33頁(yè)
文件大?。?/td> 233K
代理商： M29W800T100M1R
INSTRUCTIONSAND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, ReadElectronicSignature,Read BlockPro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structionsrequirefrom1 to6 cycles,thefirstor first
threeof whichare alwayswrite operationsused to
initiate the instruction.They are followed by either
furtherwrite cyclesto confirmthe first commandor
executethe commandimmediately.Command se-
quencing must be followed exactly. Any invalid
combinationof commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cleswhichunlockthe CommandInterface.In addi-
tion, for Erase, instruction confirmation is again
precededby the two Coded cycles.
Status Register Bits
P/E.C.statusis indicatedduring executionby Data
Polling on DQ7, detectionof Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwillautomaticallyoutputthesefive
StatusRegisterbits.TheP/E.C. automaticallysets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation,it outputsa ’0’.After com-
pletionof theoperation,DQ7will outputthe bitlast
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse forprogrammingor
after the sixth W pulse for erase. It must be per-
formedat theaddress beingprogrammedor at an
address within the block being erased. If all the
blocksselectedfor erasureareprotected,DQ7 will
be setto ’0’forabout 100
μ
s, and thenreturnto the
previous addressed memory data value. See Fig-
ure11for the DataPolling flowchart andFigure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeingerasedandthedatavalueonother
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviouras
in the normal program execution outside of the
suspendmode.
Toggle Bit (DQ6).
When Programming or Erasing
operationsare in progress,successiveattemptsto
readDQ6willoutputcomplementarydata.DQ6will
toggle following toggling of either G, or E when G
is low. The operationis completedwhen two suc-
cessivereadsyieldthesameoutputdata.Thenext
readwilloutputthebitlastprogrammedora’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100
μ
s and then
returnbacktoRead.DQ6 willbe setto ’1’ifaRead
operationisattemptedon anEraseSuspendblock.
When erase is suspended DQ6 will toggle during
programming operationsin a blockdifferent to the
block in Erase Suspend.Either E or G togglingwill
causeDQ6 to toggle. See Figure 12 for ToggleBit
flowchartand Figure 13 for ToggleBit waveforms.
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Table7. Commands
11/33
M29W800T M29W800B
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