參數(shù)資料
型號: M29W800T100M1R
廠商: 意法半導體
英文描述: Low-Power Configurable Multiple-Function Gate 6-SOT -40 to 85
中文描述: 8兆1兆x8或512KB的x16插槽,引導塊低壓單電源閃存
文件頁數(shù): 21/33頁
文件大?。?/td> 233K
代理商: M29W800T100M1R
AI02183
E
G
W
A0-A18/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWH
tGHWL
RB
tWHRL
Figure 7. WriteAC Waveforms, W Controlled
Note:
Address are latched on thefalling edge of W, Data is latched on the risingedge of W.
Duringtheexecutionof theerasebytheP/E.C.,the
memory accepts onlythe EraseSuspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasureis in progress and’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
StatusRegisterbitDQ5returns’1’iftherehasbeen
an erase failure. In sucha situation,the Togglebit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/ResetRDinstructionis necessaryinorderto
reset the P/E.C.
ChipErase(CE)Instruction.
Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address AAAAh in the Byte-widecon-
figuration or the address 5555h in the Word-wide
configurationon thethirdcycleafterthetwoCoded
cycles. The Chip Erase Confirm command 10h is
similarly writtenon thesixthcycleafter anothertwo
Codedcycles.If thesecondcommandgiven is not
an eraseconfirm or if the Codedcyclesarewrong,
the instruction aborts and the device is reset to
ReadArray.Itisnotnecessaryto programthearray
with00h firstas theP/E.C.will automaticallydothis
beforeerasingit to FFh. Readoperationsafter the
sixth rising edge of W or E output the Status
Registerbits. Duringthe executionof the eraseby
theP/E.C.,Data PollingbitDQ7returns’0’, then’1’
on completion. The Toggle bits DQ2 and DQ6
toggleduringeraseoperationandstopwhenerase
is completed.After completionthe StatusRegister
bit DQ5 returns ’1’ if there has been an Erase
Failure.
21/33
M29W800T M29W800B
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