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參數(shù)資料
| 型號： | M29W800T100M1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low-Power Configurable Multiple-Function Gate 6-SOT -40 to 85 |
| 中文描述： | 8兆1兆x8或512KB的x16插槽，引導(dǎo)塊低壓單電源閃存 |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 233K |
| 代理商： | M29W800T100M1R |
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Toggle Bit (DQ2).
This toggle bit, together with
DQ6, can be used to determine the device status
duringthe Eraseoperations.It can alsobe usedto
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend.During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
duringprogramoperationand whenerase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5).
This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
thememoryblock.In caseof anerrorinblockerase
or program,the blockin whichtheerror occuredor
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pearifa usertriesto programa’1’toa locationthat
is previouslyprogrammedto ’0’. OtherBlocksmay
stillbe used.TheerrorbitresetsafteraRead/Reset
(RD)instruction. In caseof successof Program or
Erase, the error bit will be set to ’0’.
EraseTimer Bit (DQ3).
This bit is setto ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
periodis finished,after 50
μ
s to 90
μ
s, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cyclesunlockthe CommandInter-
face.They are followedby an input commandor a
confirmationcommand.The Codedcycles consist
of writing the data AAh at address AAAAh in the
Byte-wide configuration and at address 5555h in
the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist
of writing the data 55h at address 5555h in the
Byte-wide configuration and at address 2AAAh in
theWord-wideconfiguration.IntheByte-widecon-
figurationthe addresslines A–1to A14arevalid, in
Word-wideA0 to A15arevalid,otheraddresslines
are ’don’t care’. The Coded cycles happenon first
and secondcycles of the commandwriteor on the
fourthand fifth cycles.
Instructions
See Table 8.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
commandF0h.Itcanbe optionallyprecededbythe
twoCodedcycles.Subsequentreadoperationswill
read the memory array addressed and output the
data read. A wait state of 10
μ
s is necessaryafter
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction.
This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to addressAAAAh
in the Byte-wideconfigurationor address5555hin
the Word-wide configuration for command set-up.
A subsequent read will output the manufacturer
code and the device code or the block protection
status dependingon the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresseslinesA0 andA1 areLow,thedevice code,
EEh for Top Boot, EFh for Bottom Boot is output
when A0 is Highwith A1 Low.
The AS instruction also allowsaccess to the block
protectionstatus.AftergivingtheASinstruction,A0
is set to V
IL
with A1 at V
IH
, while A12-A18 define
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protectedand a 00h if the block is not protected.
Program (PG) Instruction.
This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to addressAAAAh in the
Byte-wideconfigurationor toaddress5555h inthe
Word-wideconfigurationonthethirdcycleaftertwo
Codedcycles. Afourthwrite operationlatchesthe
Addresson the fallingedgeof Wor E andtheData
to be written on the rising edge and starts the
P/E.C.Readoperationsoutputthe StatusRegister
bits after the programming has started. Memory
programmingis made onlybywriting’0’in placeof
’1’.StatusbitsDQ6andDQ7determineifprogram-
mingison-goingandDQ5allowsverificationof any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dressbeing programmed.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in EraseSuspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Note:
1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Table10. Pollingand Toggle Bits
14/33
M29W800T, M29W800B
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