參數(shù)資料
型號(hào): M32000D4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
中文描述: 單芯片32位CMOS微機(jī)
文件頁數(shù): 13/45頁
文件大?。?/td> 535K
代理商: M32000D4
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
13
Data types
Signed and unsigned integers of byte (8 bits), halfword (16 bits), and
word (32 bits) types are supported as data in the M32R CPU instruc-
tion set. A signed integer is represented in a 2's complement format.
Data formats
Data size of a register of the M32R CPU is always a word (32 bits).
Byte (8 bits) and halfword (16 bits) data in memory are sign-extended
(the
LDB
and
LDH
instructions) or zero-extended (the
LDUB
and
LDUH
instructions) to 32 bits, and loaded into the register.
Word (32 bits) data in a register is stored to memory by the
ST
in-
struction. Halfword (16 bits) data in the LSB side of a register is stored
to memory by the
STH
instruction. Byte (8 bits) data in the LSB side
of a register is stored to memory by the
STB
instruction.
Data stored in memory can be one of these types: byte (8 bits),
halfword (16 bits) or word (32 bits).
Although the byte data can be located at any address, the halfword
data and the word data can only be located on the halfword bound-
ary and the word boundary, respectively. If an attempt is made to
access data in memory which is not located on the correct boundary,
an address exception occurs.
signed byte
(8-bit) integer
unsigned byte
(8-bit) integer
signed halfword
(16-bit) integer
0
0
0
0
0
0
7
7
15
15
31
31
S
S
S
S: sign bit
unsigned halfword
(16-bit) integer
signed word
(32-bit) integer
unsigned word
(32-bit) integer
Rn
0
31
< load >
byte
Rn
0
31
halfword
Rn
0
31
word
sign-extention (
LDB
instruction) or
zero-extention (
LDUB
instruction)
from memory
(
LDB
,
LDUB
instruction)
< store >
Rn
0
31
byte
Rn
0
31
halfword
Rn
0
31
word
to memory (
STB
instruction)
to memory (
STH
instruction)
to memory (
ST
instruction)
from memory (
LDH
,
LDUH
instruction)
from memory (
LD
instruction)
24
16
24
16
sign-extention (
LDH
instruction) or
zero-extention (
LDUH
instruction)
<data format in a register>
<data format in memory>
Fig. 7 Data type
Fig. 8 Data format
address
byte
halfword
word
+ 0
+ 1
+ 2
+ 3
0
7 8
15 16
23 24
31
byte
byte
byte
byte
halfword
halfword
word
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